A new generalized row-based global router

Swartz, W.; Sechen, C.

doi:10.1109/iccad.1993.580103

Cited by 12 publications

(8 citation statements)

References 37 publications

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“…overfiowe = lo C if de > Ce otherwise (1) The total overflow of the entire routing area is as follows. tof = overfiowe( eE-E (2) Segment. a segment is a horizontal or vertical edge line on GRG connecting its two endpoints.…”

Section: A Basic Definitions and Problem Formulationmentioning

confidence: 99%

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DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm

Cao

Tong

Xiong

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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This paper presents a fast and accurate global routing algorithm, DpRouter, based on two efficient techniques: (1) dynamic pattern routing (Dpr), and (2) segment movement. These two techniques enable DpRouter to explore large solution space to achieve better routability with low time complexity. Compared with the state-of-the-arts, experimental results show that we consistently obtain better routing quality in terms of both congestion and wire length, while simultaneously achieving a more than 30x runtime speedup. We envision that this algorithm can be further leveraged in other routing applications, such as FPGA routing. I IntroductionThe success of future integrated circuit designs requires the consideration of physical impact. Congestion-aware global routing is crucial to achieve this goal and has been proven useful in physical synthesis.Existing global routing algorithms mainly focus on congestion reduction [1][2][3][4][5][6][7][8]. Among them, [7] and [8] are two of the most recent publications with good results. Labyrinth [7] is a global router that evaluates routing results in terms of congestion and wire length. Fengshui [8] proposed the concept of amplified congestion estimation, which helped to improve both over-congestion and routing length.Some Steiner tree algorithms [9-1 1 ] even tried to improve the routability.[9] and [10] presented the idea of solving Steiner tree problem based on pre-computed lookup table.[11] proposed the concept of flexibility in the rectilinear Steiner tree (RST) problem. These tree algorithms are helpful, but the final congestion reduction still mainly relies on powerful routing algorithms.The problem of congestion-aware routing, however, is far-from being solved. This paper focuses on the routability-driven global routing problem. Our focus is congestion reduction and algorithm efficiency. The major contributions of this work are as follows:(1) An efficient dynamical pattern routing (Dpr) technique to achieve the optimal routing solution for two-pin nets.(2) A segment-move technique to extend the searching space for routability driven RST problem.

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Section: A Basic Definitions and Problem Formulationmentioning

confidence: 99%

“…Existing global routing algorithms mainly focus on congestion reduction [1][2][3][4][5][6][7][8]. Among them, [7] and [8] are two of the most recent publications with good results.…”

Section: Introductionmentioning

confidence: 99%

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm

Cao

Tong

Xiong

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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show abstract

“…We tested the router on the Primary1 circuit using three layers and the cell library from [22] [23]. The placement for Primary1 was obtained using TimberWolfSC [30] [31], and the global routing was generated by TimberWolfGR [29]. Figure 7 shows the complete routing solution of a Primary1 test channel with density=15 routed using only one channel track.…”

Section: Resultsmentioning

confidence: 99%

A gridless multi-layer router for standard cell circuits using CTM cells

Tseng¹,

Sechen²

Proceedings European Design and Test Conference. ED &Amp; TC 97

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“…This is more important when the number of leiif cells in a bit-slice is large which is typically the case in we attempt to route each of the control signals in minimum number of channels and preserve the dataflow present in the design. For global routing of multiple nets we propose a window-based heuristic which to the best of our knowledge has not been applied to the global routing problem before (see [9] for references). This technique generates an efficient global routing without rip-uprerouting of nets and cm be easily integrated into Spanninglsteiner-tree [9] based global routing algorithms.…”

Section: Introductionmentioning

confidence: 99%

“…For global routing of multiple nets we propose a window-based heuristic which to the best of our knowledge has not been applied to the global routing problem before (see [9] for references). This technique generates an efficient global routing without rip-uprerouting of nets and cm be easily integrated into Spanninglsteiner-tree [9] based global routing algorithms.…”

Section: Introductionmentioning

confidence: 99%

Layout synthesis for datapath designs

Buddi¹,

Chrzanowska-Jeske²,

Saxe³

Proceedings of EURO-DAC. European Design Automation Conference

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DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and e c i e n t heuristics for placing the cells in a bit-slice, such that the regulariv of datapath circuits is preserved and the number of channels occupied by a control signal is minimized. In addition, we propose a novel window-based heuristic for global routing of multipin nets. VHDL interface makes DPLAYOUT a general tool which can be easily integrated with any high-level synthesis system. This paper describes the heuristics developed for placement and global routing of a single bit-slice. We compared the area and run-time efficiency of the proposed heuristics with conventional methods and the results show a significant improvement.

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A new generalized row-based global router

Cited by 12 publications

References 37 publications

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm

A gridless multi-layer router for standard cell circuits using CTM cells

Layout synthesis for datapath designs

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