High-resolution transmission electron microscopy and scanning tunneling microscopy have been combined to examine the structure of the thin "native" oxide that forms on silicon surfaces at room temperature. Differences in the cleaning procedures for silicon wafers may affect the morphology of this oxide and critically influence further processing on the silicon substrates. An etch that ended with a dip in hydrofluoric acid provided a thinner oxide and a lower interface step density than did a sulfuric peroxide treatment. The availability of complementary information from high-resolution transmission electron microscopy and scanning tunneling microscopy is discussed.

We have developed a technique for growth of thin oxides (80–90Å) with an intermediate annealing step. The oxides exhibit a tight distribution in breakdown voltage measurements leading to defect density less than 5/cm2, intrinsic breakdown field of 12 MV/cm, and a value of less than 1×1010/cm2‐normaleV for interface trap density in midgap. The inferior electrical properties of thin oxides grown by conventional methods in dry oxygen with Ar dilution have been correlated with normalSi‐SiO2 interface roughness using high resolution transmission electron microscopy. The intermediate annealing process may be used to improve the endurance and retention properties of EEPROM devices and alleviate the degradation of thin oxides in short‐channel MOS devices.

Mit dem Ziel einer Eigenschaftsverbesserung von Halbleiterbauteilen wird gezeigt, daß für das Aufwachsen dünner Oxidschichten (80‐90 Å) auf Si eine Zstufige Oxidation mit dazwischengeschaltetem Tempern bei 1050°C günstiger ist als Tempern nach vollendetem Oxidwachstum.

Copper is shown to be inadvertently introduced as an impurity during the formation of silicon-on-insulator structures by high fluence oxygen implantation. Postimplantation annealing causes the copper to diffuse from the silicon surface through the oxide and be preferentially gettered to dislocations that originate at the oxide-silicon substrate interface. The concentration of copper in the silicon surface layer is reduced by a factor of two, and no copper remains in the buried oxide layer. Sufficient gettering occurs for the fabrication of fully functional n-channel metal-oxide-semiconductor fieldeffect-transistors, with, however, a low yield. Also, the effective carrier mobility in the inversion layer of the transistors is severely degraded, and this is attributed primarily to copper retained in that layer.