This paper describes the design and fabrication of planarized multilayer atom chips for an ultrahigh-vacuum system in atomic physics experiments. A fabrication process is developed to define micrometer-scale wire patterns on a silicon substrate and wires are plated by copper electroplating. SU-8 is chosen as the isolation layer between the upper and bottom wires, and its thickness, surface flatness and surface roughness (Ra = 5 nm) are controlled by the chemical–mechanical planarization process. A reflectivity of nearly 90% is measured on the chip surface; thus, the former method of attaching a silver mirror is unnecessary (Du et al 2004 Phys. Rev. A 70 053606). A heat dissipation copper block is incorporated in our chip design to increase the sustainable current densities of upper wires of more than 3.8 × 105 A cm−2. Results show the improvement of 55.74%, compared with the nonheat dissipation design (2.44 × 105 A cm−2), and thus meeting the requirements for chip-based atom trapping experiments.

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