This paper presents an enhanced Marchand balun that offers excellent amplitude and phase balance performance. The enhanced Marchand balun is designed using compensated coupled lines. It employs capacitive compensation, a renowned technique for compensating the unequal even-and odd-mode phase velocities encountered in parallel-coupled microstrip. Analysis carried out in this study has proven that the finite directivity of coupled lines significantly affects the balun Performance. The proposed capacitively-compensated Marchand balun is demonstrated at 2.1GHz and has offered excellent results.
The 3 D interconnect technology with Thru Silicon Via (TSV) have gained tremendous advancement in recent years. Final adoption of TSV technologies requires a robust and cost competitive TSV processes. Sidewall plated TSV with polymer filling can reduce half of total process steps from TSV copper (Cu) seed deposition to front-via1 expose. TSV plating time can be reduced ~ 60% for sidewall plated TSV with polymer filling. Costly Cu removal process through chemical mechanical polishing (CMP) can be skipped in sidewall plated TSV with polymer filling process. Wafer warpage and bow for sidewall plated TSV with polymer filling were shown to be ~70% and ~94%, respectively lower than solid Cu filled TSV. Thermal-mechanical simulation show 20% and 42% reduction of shear and bending stress respectively in the case of sidewall plated TSV with polymer filling.
IntroductionThe concept of 3D packaging using TSV stacking is one of the most promising technologies. It can extend Moore's Law by stacking and shortening the connection path between memory and logic [2]. Due to the increased in functional integration requirements, more and more assembly house and wafer foundries are looking into 3D TSV technology, which allows stacking of Large Scale Integrated Circuits (LSIs) thereby enabling products to be made smaller with more functionality. 3D technology realizes miniaturization by 300-400% compared to the conventional packaging [3].Although the electrical benefits are greatly increasing in stacked IC packages, their corresponding thermo-mechanical problems are raising as well. This includes problem of coefficient of thermal expansion (CTE) mismatch between copper (~17.5x10 -6 / o C) and silicon (~2.5x10 -6 / o C), heat dissipation, induced stresses, interfacial delimitation, via cracking and so on [1,4,5,6]. Wafer warpage and stress is one of challenge within TSV process integration. Local TSV stress directly decides the TSV performance and reliability. We will focus on wafer warpage and stress comparison for the solid and sidewall plated TSV with polymer filling in this paper. Simulation results were used for the comparison of the local stress in two different approaches.
A Ka-band high power amplifier MMIC developed from 0.18μm gate-length AlGaN/GaN HEMT on SiC is presented. The MMIC chip was measured on-wafer across 29GHz to 31GHz under pulsed bias condition. At VDD=28V, the MMIC achieved an output power of 19W to 21W. To the authors' best knowledge, this is the highest output power ever reported for GaN high power amplifier MMIC at Ka-band. The 2-stage amplifier GaN MMIC has 10dB linear gain and a die-size of 4.0mm x 5.5mm. The MMIC can realize high power Solid-State Power Amplifier (SSPA) for Ka-band.
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