InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54 mV/dec SS is achieved at 100 pA/lm over a drain voltage range of 0.2-0.5 V. The SS remains sub-60 mV/dec over 1.5 orders of magnitude of current at room temperature. Trap-Assisted Tunneling (TAT) is found to be negligible in the device evidenced by low temperature dependence of the transfer characteristics. Equivalent Oxide Thickness (EOT) is found to play the major role in achieving sub-60 mV/dec performance. The EOT of the demonstrated devices is 0.8 nm.

In this work, the impact of the diameter on vertical nanowire tunnel field effect transistors is analyzed focusing on the conduction mechanism and analog parameters, considering different conduction regimes. The diameter influence is investigated using experimental and simulation data. The impact of the diameter on the analog parameters is analyzed, considering both weak and strong conduction. For a smaller diameter, the impact of band-to-band tunneling (BTBT) on the device characteristics increases, showing opposite trends for weak and strong conduction. For strong conduction, a degradation of the intrinsic voltage gain occurs for very small diameters, because the device has less available area for the occurrence of tunneling. For weak conduction, the reduction of the diameter increases the BTBT along the channel/source junction without showing this degradation. Index Terms-Analog performance, band-to-band tunneling (BTBT), conduction mechanism, tunnel field effect transistor (TFET). I. INTRODUCTION T UNNEL field effect transistors (TFETs) are devices in which the designed conduction mechanism is the band-to-band tunneling (BTBT) [1]. TFETs are candidate solutions for low-power/low-voltage applications due to their capability to overcome, at room temperature, the theoretical silicon (Si) MOSFET limit of 60 mV/dec for the subthreshold swing [2]-[4].

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In this work, the impact of the nanowire TFET diameter on analog parameters in "weak" and "strong inversion" conditions is analyzed. Its relation with the current conduction mechanism is also studied. A comparison of the analog performance among TFETs doped with different source doping profile (abrupt and nonabrupt) and MOSFETs was experimentally realized for larger diameter nanowires. Additionally the TFET evaluation was extrapolated for smaller diameters by numerical simulation. The transistor efficiency and the Early voltage were considered in order to calculate the intrinsic voltage gain (AV). Both effects influence AV degradation for TFETs with smaller diameters biased in "weak inversion". While larger TFET nanowires show better AV than MOSFETs under "strong inversion" bias, narrower nanowires present potentialities for low power and low voltage applications, since their AV is better than the corresponding values for larger diameters TFET nanowires under "weak inversion" bias.