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The balance winding of the transformer is a compact and flexible technique for the common-mode (CM) noise reduction of isolated power converters. A proper design of the grounding and turn number of the balance winding will generate an inverse displacement current to balance the CM noise flowing through the transformer. However, a trial and error process to find the optimum design is necessary for practical applications due to the unexplored source of calculation errors. In this paper, a quantitative analysis method of CM currents flowing through all the paths between windings is proposed for error quantifications. Based on an interleaved transformer, the capacitances are extracted with the help of electric field simulations, and the contribution of each path to the CM noise is analysed. Although the paths between adjacent layers are dominant in the CM noise, it is proved that ignoring non-adjacent inter-layer paths will lead to calculation errors due to the high voltage difference even with low capacitances. As both the application and verification of the proposed quantitative analysis method, the accurate evaluation of noise reduction effects and determination of the optimum balance winding turns can be achieved in experiments.

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