Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, the implementation of the layered architecture is not always straightforward because of the memory access conflicts in the a-posteriori information memory. In this paper, we focus our attention on a particular type of conflict introduced by the existence of multiple diagonal matrices in the DVB-T2 parity check matrix structure. We illustrate how the reordering of the matrix reduces the number of conflicts, at the cost of limiting the level of parallelism. We then propose a parity extending process to solve the remaining conflicts. Fixed point simulation results show coherent performance without modifying the layered architecture.

This paper proposes a unified framework to describe check node architectures of Non-Binary LDPC decoders. Forward-Backward, Syndrome-Based and Pre-sorting approaches are first described. Then, they are hybridized in an effective way to reduce the amount of computation required to perform a check node. This work is specially impacting check nodes of high degrees (or high coding rates). Results of 28 nm ASIC post-synthesis for a check node of degree 12 (i.e. code rate of 5/6 with a degree of variable equal to 2) are provided for NB-LDPC over GF(64) and GF(256). While simulations show almost no performance loss, the new proposed Hybrid implementation check node increases the hardware and the power efficiency by a factor of six compared to the classical Forward-Backward architecture. This leads to the first ever reported implementation of a degree 12 check node over GF(256) and these preliminary results open the road to high decoding throughput, high rate, and high order Galois Field NB-LDPC decoder with reasonable hardware complexity.