Hybrid Check Node Architectures for NB-LDPC Decoders

Abstract

This paper proposes a unified framework to describe check node architectures of Non-Binary LDPC decoders. Forward-Backward, Syndrome-Based and Pre-sorting approaches are first described. Then, they are hybridized in an effective way to reduce the amount of computation required to perform a check node. This work is specially impacting check nodes of high degrees (or high coding rates). Results of 28 nm ASIC post-synthesis for a check node of degree 12 (i.e. code rate of 5/6 with a degree of variable equal to 2) are provided for NB-LDPC over GF(64) and GF(256). While simulations show almost no performance loss, the new proposed Hybrid implementation check node increases the hardware and the power efficiency by a factor of six compared to the classical Forward-Backward architecture. This leads to the first ever reported implementation of a degree 12 check node over GF(256) and these preliminary results open the road to high decoding throughput, high rate, and high order Galois Field NB-LDPC decoder with reasonable hardware complexity.

Parallel CN-VN processing for NB-LDPC decoders

“…PIPELINED CN-VN UNIT This section presents a pipelined architecture able to perform a CN of degree d c = 12 and its 12 associated VNs every Clock Cycle (CC). Based on the Hybrid (H)-CN architecture [11], an optimized version of the CN architecture for the 5/6rate codes (d v = 2) is described and merged to the VN to form the innovative CN-VN unit.…”

Rate-adaptive Inner Code for Non-Binary Decoders

“…3 1111010110010000 α 3 4 1110101100100001 α 4 5 1101011001000011 α 5 6 1010110010000111 α 6 7 0101100100001111…”

“…However, designing a rate-adaptive NB-decoder along with NB codes is still a complex task. In fact, most NB decoder implementations are optimized for a single code rate [6] [7] [8]. One way to get around the problem is by giving the rate-adaptive task to an inner code.…”

The Best, The Requested, and The Default Non-Binary LDPC Decoding Algorithm

“…Another EMS-based approach is the Syndrome-Based (SYN) decoder [5], SYN decoder helps in achieving a high level of parallelism and higher throughput in the CN unit. In [6], a hybrid approach is proposed that combines both the FWBW and the SYN architectures. The hybrid architecture achieved the lowest-reported number of exchanged messages using the EMS algorithm (6 candidates as input to CN and 20 candidates as output).…”

“…The last column sums the number of GF and LLR elements exchanged per edge and per iteration. For a code on GF(64) with r = 5/6 and a CN degree of connectivity d c of 12, the lowest number of the exchanged elements among the studied scheme is 48 (Table.I) achieved by the hybrid EMS decoder[6], whereas the total number of exchanged elements per edge in the BRD decoder is 17. Furthermore, the number of the memory resources reserved for M V 2C is greatly reduced from d c × q down to d c × 7 and from d c ×q down to d…”