Parallel CN-VN processing for NB-LDPC decoders

Harb, Hassan; Marchand, Cédric; Conde-Canencia, Laura; Boutillon, Emmanuel; Ghouwayel, Ali Chamas Al

doi:10.1109/sips52927.2021.00024

Cited by 2 publications

(4 citation statements)

References 12 publications

(18 reference statements)

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“…NB-LDPC codes still remain a high complexity of decoder, although they give a robust performance compared to the conventional turbo-codes and binary LDPC codes, especially in high order modulation as indicated in [26]. Hence, it is not a possible option for transmitting short-packet FD transmission, as it fails to obtain the required level of accuracy in estimating SI channel.…”

Section: Proposed Nb-ldpc Blind Feedback Modelmentioning

confidence: 99%

Non-binary codes approach on the performance of short-packet full-duplex transmissions

Vuong,

Trang,

Nguyen

et al. 2024

IJECE

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This paper illustrates the enhancement of the performance of short-packet full-duplex (FD) transmission by taking the approach of non-binary low density parity check (NB-LDPC) codes over higher Galois ﬁeld. For the purpose of reducing the impacts of self-interference (SI), high order of modulation, complexity, and latency decoder, a blind feedback process composed of channels estimation and decoding algorithm is implemented. In particular, this method uses an iterative process to simultaneously suppress SI component of FD transmission, estimate intended channel, and decode messages. The results indicate that the proposed technique provides a better solution than both the NB-LDPC without feedback and the binary LDPC feedback algorithms. Indeed, it can signiﬁcantly improve the performance of overall system in two important factors, which are bit-error-rate (BER) and <a name="_Hlk155778233"></a>mean square error (MSE), especially in high order of modulation. The suggested algorithm also shows a robustness in reliability and power consumption for both short-packet FD transmissions and high order modulation communications.

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Section: Proposed Nb-ldpc Blind Feedback Modelmentioning

confidence: 99%

Non-binary codes approach on the performance of short-packet full-duplex transmissions

Vuong,

Trang,

Nguyen

et al. 2024

IJECE

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“…In this paper, we extend the work presented in [25] to design an ultra-throughput decoder that can reach an average decoding throughput of 14 Gbits/s at high Signal to Noise Ratio (SNR). Besides that, more algorithmic and hardware decoding block details are shown along with a global timing diagram of the decoder.…”

Section: Introductionmentioning

confidence: 95%

“…Every RAM i , i = 0, … , 11 , stores 24 extrinsic messages of 12 successive VNs, with each VN connected to a CN in L 1 and a CN in L 2 . For instance, RAM 2 stores the extrinsic messages associated to VN 24 , VN 25 0 is associated to VN 0 in the second layer and hence it will be stored in RAM 0 [12]; U b 1 is associated to VN 12 and hence it will be stored in RAM 1 [23], ...; U b 11 is associated to VN 132 and it will be stored in RAM 11 [13]. Therefore, each RAM i requires its own write address A w i , i = 0, … , 11 .…”

Section: Memory Blocksmentioning

confidence: 99%

“…Moreover, an unexpected result is found out where the proposed architecture almost halves the memory bandwidth compared to a classical binary LDPC code. The design includes the presorting technique and an innovative unit that processes both the CNs and Variable Nodes (VN) in a fully pipelined architecture [25]. This architecture is called "Full Parallel Hybrid Check Node" (FPHCN) in this paper.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

Harb

Ghouwayel

Conde-Canencia

et al. 2022

J Sign Process Syst

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This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one row of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N, K) = (144, 120) symbols over GF(64). The synthesis results on a 28-nm technology show that for a 0.789 M NAND-gates complexity complexity, the architecture reaches a decoding throughput of 0.9 Gbps with 30 decoding iterations. Compared to the 5G binary LDPC code of the same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of $$10^{-3}$$ 10 - 3 .

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Parallel CN-VN processing for NB-LDPC decoders

Cited by 2 publications

References 12 publications

Non-binary codes approach on the performance of short-packet full-duplex transmissions

Non-binary codes approach on the performance of short-packet full-duplex transmissions

Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

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