We discuss the room temperature annealing of Floating Gate errors in Flash memories with NAND and NOR architecture after heavy-ion irradiation. We present the evolution of rough bit errors as a function of time after the exposure, examining the annealing dependence on the particle LET, cell feature size, and for Multi Level Cells, on the program level. The results are explained based on the statistical properties of the cell threshold voltage distributions before and after heavy-ion strikes

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Heavy ions typical of the space environment have energies which exceed by orders of magnitude those available at particle accelerators. In this paper we are irradiating state of the art Floating Gate memories by using a medium energy (SIRAD) and a high energy (RADEF) facilities. The corruption of stored information decreases when increasing ion energy. The proposed model deals with the broader track found for higher energy ions. Implications for testing procedures and for reliability considerations are discussed.