Myriad structures for stacking chips, power devices, smart cards, and thin substrates for processors have one thing in common: thin silicon. Wafer thinning will soon be an essential process step for most of the devices fabricated and packaged henceforth. The key driving forces for thinned wafers are improved heat dissipation, three-dimensional stacking, reduced electrical resistance, and substrate flexibility. Handling of thin and ultrathin substrates however is not trivial because of their fragility and tendency to warp and fold. The thinned substrates need to be supported during the backside grinding process and through the subsequent processes such as lithography, deposition, etc. Using temporary adhesives to attach the processed device wafer to a rigid carrier wafer offers an efficient solution. The key requirements for such materials are ease of application, coating uniformity with minimal thickness variation across the wafer, good adhesion to a wide variety of surfaces, thermal stability in processes such as dielectric deposition and metallization, and ease of removal to allow high throughput. An additional requirement for these materials is stability in harsh chemical environments posed by processes such as etching and electroplating. Currently available materials meet only a subset of these requirements. None of them meet the requirement of high-temperature stability combined with ease of removal. We have developed adhesives that meet a wide range of post-thinning operating temperatures. Additionally, the materials are soluble in industry-accepted safe solvents and can be spin-applied to required thicknesses and uniformity. Above all, the coatings can be removed easily without leaving any residue. This paper reports on the development of a wide range of temporary adhesives that can be used in wafer thinning applications while applying both novel and conventional bonding and debonding methods.

In this paper we study the uniformity of up to 150 mm in diameter wafer-scale III-V epitaxial transfer to the Si-on-insulator substrate through the O 2 plasma- enhanced low-temperature (300°C) direct wafer bonding. Void-free bonding is demonstrated by the scanning acoustic microscopy with sub-µm resolution. The photoluminescence (PL) map shows less than 1 nm change in average peak wavelength, and even improved peak intensity (4% better) and full width at half maximum (41% better) after 150 mm in diameter epitaxial transfer. Small and uniformly distributed residual strain in all sizes of bonding, which is measured by high-resolution X-ray diffraction Omega2Theta mapping, and employment of a two-period InPInGaAsP superlattice at the bonding interface contributes to the improvement of PL response. Preservation of multiple quantum-well integrity is also verified by high-resolution transmission electron microscopy.

Wafer thinning has been effectively used to improve heat dissipation in power devices and to fabricate flexible substrates, small chip packages, and multiple chips in a package. Wafer handling has become an important issue due to the tendency of thinned wafers to warp and fold. Thinned wafers need to be supported during the backgrinding process, lithography, deposition, etc. Temporary wafer bonding using removable adhesives provides a feasible route to wafer thinning. Existing adhesives meet only a partial list of performance requirements. They do not meet the requirements of high-temperature stability combined with ease of removal. This paper reports on the development of a wide range of temporary adhesives to be used in wafer thinning applications that use both novel and conventional bonding and debonding methods. We have developed a series of novel removable high-temperature spin-on adhesives with excellent bonding properties and a wide range of operating temperatures for bonding and/or debonding to achieve a better processing window.

The packaging of an IC chip (die) encompasses a multitude of assembly and packaging issues. The important factors for packaging technology are costs of IC packaging, the impact of the package on the circuit and system performance, and on the reliability of the package. Wafer level packaging technology has shown to be a promising solution for future IC generations. This paper reviews wafer level bumping process and it's requirement for thick resist coating and full field aligned exposure. 3D interconnect technolosly is a viablesolution for increasing electronic device functional density and reducing total packaging costs'. The critical issue is the ability to align and bond with precision, one micron or less, two silicon wafers or a silicon wafer to another substrate. For CMOS devices this technology will be applied for chip-scale packaging and also for advanced 3D interconnect processes. In this paper we will describe a new approach to wafer-to-wafer alignment using alignment targets at the bond interface i.e. face to face wafer alignment (SmartViewTM) that relies on precision alignment positioning systems to register and align wafers with one micron or better precision.

An ever increasing need exists for thick resist layers in the processing of MEMS and for advanced packaging. Applications in the MEMS field include bulk micromachining, surface micromachining, and the actual creating of active device structures. For advanced packaging, the applications are in redistribution and passivation layers, and micromolds for metal bumps. The various applications can require resist layer thicknesses up to and exceeding 1000 µm. In order to properly achieve these thicknesses, appropriate coating materials were developed by manufacturers. These materials include AZ P4620, Shipley SPR220, AZ PLP100XT, JSR THB 611P, and SU-8. Finally, equipment was developed to handle these materials, in the form of specialized coating equipment and contact/proximity aligners.