No abstract

The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase-locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 μm CMOS technology. The calibration time is 32.8 μs, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm 2 .

-A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5μA current mismatch in CP. It was designed in a standard 0.13μm CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38mW with 1.5V power supply and effective area is 0.1804mm 2 .

A fully integrated three stage cascaded radio frequency variable gain amplifier (RFVGA) linearly controlled by exponential current generation circuit is presented. The gain control is unequally distributed in each stage for noise figure (NF) and linearity performance. The dB-linear gain control is realized using pseudo exponential current generated by CMOS current summing circuit with a voltage to current converter. The RFVGA has over 50 dB dynamic range. Gain changes from -38.5 to 16.8 dB according to control voltage that varies from 0.5 to 1.8 V. It operates at 0.95–2.15 GHz. This design is implemented in 0.18 μm CMOS technology.

A fast transient-response digital low-dropout regulator (D-LDO) is presented. To achieve fast-transient time, a VSSa generator and a coarsefine power-MOS array techniques are proposed. The proposed D-LDO is implemented in a 65 nm CMOS technology with a die area of 0.067 mm 2. The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5 mA to 120 mA, and the step-down time is 0.1 us at 1.2 V of supply voltage. Moreover, the voltage spikes are less than 190 mV.