This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are 1) the writeand-verify (WAV) writing of four-level resistance states and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called resistance drift) and 4) of resistance increase after thermal annealing. With taking into account of them, we realized a two-bit cell operation in diodeswitch phase change memory cells with 90nm technology. All of four resistance levels are highly write endurable and immune to write disturbance above 10 8 cycles, respectively. In addition, they are nondestructively readable above 10 7 read pulses at 100ns and 1uA. IntroductionPhase-change random access memory (PRAM) is most promising to realize a multi-level cell (MLC) operation because it has very wide range of resistance across two orders of magnitude or the higher, with respect to writing current. According to the PRAM road map [1], it is expected that highest memory densities of PRAM become comparable to conventional memories such as NOR Flash and DRAM in coming years when MLC operation is fully accomplished. In this paper, we systematically investigated a four-level (two-bit) cell operation in diode-switch phase change memory cells with 90nm technology and discussed its possibilities and issues as well.

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We have proposed an integrated method to realize MLC PRAM at 45nm technology node and beyond. It includes reset initialization, Toff skew write, and 2bit write to enhance write-and-verify speed, and 3-cell reference scheme to cope with cell variation due to resistance drift and temperature change. Based on the proposed methods, write throughput can be increased up to SLC level with robust read operation. (Keywords: PRAM, MLC, speed and reference cell) IntroductionPRAM is considered as one of the most possible candidates to follow NOR, NAND and DRAM due to its better scalability [1]. The wide resistance range also makes it possible to realize its MLC version [2], which will be more attractive in the market due to low cost. In the paper, we have proposed an integrated scheme for MLC PRAM, which enhances write throughput and secures a reliable read operation against resistance drift and temperature change.

This paper presents a disk-type capacitive sensor for the simultaneous measurement of five-dimensional motions of a target. The sensor detects both air gap and mutual area changes for these five-dimensional motions. In addition, the sensor is manufactured with a printed circuit board (PCB), which reduces manufacturing costs. The sensor is optimally designed through both an error analysis of possible mechanical errors and a finite element analysis of the parasitic capacitances. Furthermore, the sensor can correct measurement errors due to the initial misalignment between the sensor and the target. A prototype PCB sensor, electronics and a test rig were built, and the effectiveness of the developed sensor was proved through experiments.