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018ChemInform Abstract By the aid of more than 100 alloys a detailed investigation is presented on the whole liquidus surface in the title system. An isothermal section at 703 rc C is also determined. The main feature of the ternary system is the occurrence of a centrally placed phase Cu2TiZr.

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Low cycle fatigue of solder joints is one of the major kinds of failures in second level interconnections of an electronic package. The fatigue failure is caused by thermal strains which are created from a mismatch of coefficients of thermal expansion (CTE) that occurs between two levels of packaging. As the package approaches smaller dimensions, measurements of thermal strains in the solder interconnections become very difficult. In this paper, moire interferometry technique was applied to evaluate the thermal strains in the second level interconnections for both conventional pin-in-hole (PIH) packages and surface mount components. The coefficient of thermal expansion of each component was measured. Thermal strain distributions in the solder interconnections were determined, and reliability issues were discussed. The strains in solder joints of the PIH components were much higher than those of the stacked surface mount components. Even though the surface mount components had a lower inherent strength, their overall mechanical reliability was much higher since they had practically no localized strain concentrations.

A large area reconfigurable imaging array for research purposes is being developed with co-integrated cMUTs and control electronics. The goal is a 2.5cm 2D tileable module with >16,000 transducer sub-elements spaced at a pitch of 185um in X and Y dimensions. As a prototype demonstration of some of the goals of this effort, a multi-row linear array using cMUTs and external multiplexing electronics was designed and fabricated. In this paper the challenges of trenched cMUT attach to a laminate interposer as part of a tileable module will be discussed. The architecture of the tileable module build-up for manufacturability, reliability, acoustic planarity, and reduced spacing between tiles and cMUT chips will also be addressed. Finally, a first prototype will be shown and experimental acoustic results with the new cMUT-based probe will be presented.