High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale. A scaling trend study revealed that the scaled CNT-based devices, which use graphene contacts, can operate much faster and at much lower supply voltage (0.4 versus 0.7 volts) and with much smaller subthreshold slope (typically 73 millivolts per decade). The 5-nanometer CNT FETs approached the quantum limit of FETs by using only one electron per switching operation. In addition, the contact length of the CNT CMOS devices was also scaled down to 25 nanometers, and a CMOS inverter with a total pitch size of 240 nanometers was also demonstrated.

An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.

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Carbon nanotube (CNT)-based electronics are a potential candidate to replace silicon complementary metal-oxide-semiconductor (CMOS) technology, which will soon meet its performance limit at the 7 or 5 nm technology node 1,2 . Prototype device studies using individual CNTs have shown that nanotube electronics have the potential to outperform Si CMOS technology in both performance and power consumption [3][4][5][6] , and are even close to the theoretical limits for all field-effect-transistor(FET)-based binary switches 7,8 . Recently, FETs were fabricated using aligned CNT arrays, and shown to have a higher channel conductance (at a lower bias) than that of Si CMOS FETs 9 . However, the key performance metrics reported for such CNT FETs, including on-state current density (I on ) and transconductance (g m ), are still substantially lower than those of conventional Si CMOS FETs at the same characteristic length [9][10][11][12][13] . The ideal material system for high-performance CNT electronics has been identified as a parallel array film of intrinsic pure semiconductor single-walled nanotubes of a single chirality with a diameter of approximately 1.3 nm and no defects, and a tube-tube spacing of 5-8 nm (ref. 14 ). Although such an ideal material system is yet to be realized, many breakthroughs in the purification and controlled synthesis of CNTs have been made in recent years [15][16][17][18][19] , suggesting the possibility of achieving the required nanotube purity and array density before 2020 14 . Using randomly oriented or aligned CNT array films, various types of CNT thin-film FETs have been fabricated [9][10][11][12][13] . However, hindered by the limited performance of nanotube FETs, the operation speed of CNT integrated circuits (ICs) 20-31 typically falls short of their expected terahertz potential, and that achieved by Si CMOS circuits (gigahertz), by several orders of magnitude. Notably, CNT-based ring oscillators (ROs) with an oscillation frequency (f o ) of 282 MHz have recently been reported 32 . However, CNT-thin-film-based ICs typically have a working frequency of less than 1 MHz, which might be useful for flexible electronics, but is not suitable for mainstream high-performance CMOS technology 33 . In this study, we used a randomly oriented CNT film to build CNT FETs and ICs, fabricating, in particular, five-stage ROs with f o of up to 5.54 GHz. The random CNT film is essentially the same as a network film, but here we used the term 'random film' to emphasize that our FETs are contact dominated and have a different transport mechanism to that of junction-dominated network-type FETs 34,35 . In principle, aligned CNT arrays would provide better device performance, but it remains a challenge to obtain wafer-scale aligned CNT arrays with high uniformity, high density and high semiconductor purity for constructing high-performance ICs. Although it is not the ideal scheme, the FET-and IC-based random CNT film can nevertheless provide a feasible demonstration to assess the floor-level performance (f...

The air-stable and high-mobility two-dimensional (2D) Bi2O2Se semiconductor has emerged as a promising alternative that is complementary to graphene, MoS2, and black phosphorus for next-generation digital applications. However, the room-temperature residual charge carrier concentration of 2D Bi2O2Se nanoplates synthesized so far is as high as about 1019–1020 cm–3, which results in a poor electrostatic gate control and unsuitable threshold voltage, detrimental to the fabrication of high-performance low-power devices. Here, we first present a facile approach for synthesizing 2D Bi2O2Se single crystals with ultralow carrier concentration of ∼1016 cm–3 and high Hall mobility up to 410 cm2 V–1 s–1 simultaneously at room temperature. With optimized conditions, these high-mobility and low-carrier-concentration 2D Bi2O2Se nanoplates with domain sizes greater than 250 μm and thicknesses down to 4 layers (∼2.5 nm) were readily grown by using Se and Bi2O3 powders as coevaporation sources in a dual heating zone chemical vapor deposition (CVD) system. High-quality 2D Bi2O2Se crystals were fabricated into high-performance and low-power transistors, showing excellent current modulation of >106, robust current saturation, and low threshold voltage of −0.4 V. All these features suggest 2D Bi2O2Se as an alternative option for high-performance low-power digital applications.