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A low power phase locked loop (PLL)-based modulator for wireless sensor application is presented in this paper. The modulator adopts two-point modulation architecture in high-pass and low-pass paths of PLL; it modulates the divide ratio through sigma-delta modulator and VCO frequency tuning port simultaneously. An interleave-biased varactor pair is used to linearize the frequency tuning curve of the VCO. Besides, to achieve the desired frequency deviation of 500 kHz, we use a structure with parallel and serial capacitances in combination with tuning varactors. This topology does not need the minimum size varactor, which is sensitive to process variation and mismatch. Implemented in standard 0.18-μm CMOS process, the modulator achieves a 5.2% FSK error for 2 Mbps data rate without using any auto-calibration circuit, consuming 7.8-mW power. Loop filter and crystal are the only off-chip components.

This paper presents a low power VCO based ADC with asynchronous sigma-delta modulator (ASDM). A prototype is designed in 65nm CMOS technology with a measured performance of 54.3dB SNDR and 68dB SFDR over 8MHz bandwidth while consuming 2.8mW from a 1.2V supply.I.