Low phase noise and linear gain VCO using self-switched biasing

Chen, Nan; Huang, Lu; Wang, Chenluan; Yan, Yuepeng; Lin, Fujiang

doi:10.1109/rfit.2011.6141786

Cited by 7 publications

(4 citation statements)

References 9 publications

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“…Here, V tune is the control voltage of the varactor. This equation means that the linearity of the varactor (K VAR = ∂C=∂V tune ) directly affects the linearity of the VCO, 14) and the variation in C −3=2 K VAR should be minimized for the VCO with high linearity. Figures 3(a) and 3(b) show the wellknown varactor configurations, which are the inversion-mode MOS varactor (I-MOS) and accumulation-mode MOS varactor (A-MOS).…”

Section: Proposed Back-gate Tuning Techniquementioning

confidence: 99%

“…[8][9][10][11][12][13] For example, a limited output voltage swing causes phase noise deterioration, and a small active control voltage range of the VCO for frequency tuning causes a large non-linearity to maintain a certain frequency tuning range because the frequency-voltage curve of the VCO is steep and the slope (K VCO ) varies markedly in a different control voltage region. 14) The non-linearity of the VCO may also deteriorate the PLL stability and phase noise characteristics.…”

Section: Introductionmentioning

confidence: 99%

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0.5 V 5.8 GHz highly linear current-reuse voltage-controlled oscillator with back-gate tuning technique

Ikeda¹,

Lee²,

Ito³

et al. 2015

Jpn. J. Appl. Phys.

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In this paper, we present a voltage-controlled oscillator (VCO), which achieves highly linear frequency tuning under a low supply voltage of 0.5 V. To obtain the linear frequency tuning of a VCO, the high linearity of the threshold voltage of a varactor versus its back-gate voltage is utilized. This enables the linear capacitance tuning of the varactor; thus, a highly linear VCO can be achieved. In addition, to decrease the power consumption of the VCO, a current-reuse structure is employed as a cross-coupled pair. The proposed VCO was fabricated using a 65 nm Si complementary metal oxide semiconductor (CMOS) process. It shows the ratio of the maximum VCO gain (KVCO) to the minimum one to be 1.28. The dc power consumption is 0.33 mW at a supply voltage of 0.5 V. The measured phase noise at 10 MHz offset is −123 dBc/Hz at an output frequency of 5.8 GHz.

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Section: Proposed Back-gate Tuning Techniquementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

0.5 V 5.8 GHz highly linear current-reuse voltage-controlled oscillator with back-gate tuning technique

Ikeda¹,

Lee²,

Ito³

et al. 2015

Jpn. J. Appl. Phys.

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show abstract

“…Based on the idea, a low phase noise LC oscillator is proposed, which not only reduces intrinsic flicker noise of tail current source but also suppresses the upconversion of flicker noise from cross-coupled pair without consuming additional power, and the dependence of power dissipation and switching swing in self-switched biasing is removed. Part of the work has been presented in [16], while this paper details with phase noise analysis and optimization.…”

Section: Introductionmentioning

confidence: 99%

Reduction of 1/f 3 phase noise in LC oscillator with improved self-switched biasing

Chen

Diao

Huang

et al. 2015

Analog Integr Circ Sig Process

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According to the discussion of noise sources and up-conversion mechanisms of flicker noise, an LC oscillator with improved self-switched biasing and decoupling capacitor is presented. To minimize the 1/f 3 phase noise, both source noise and conversion gain of flicker noise are desirable to reduce, rather than only one way in previous works. Flicker noise from tail-biasing transistors is reduced by self-switched biasing technology, and the upconversion of flicker noise from cross-coupled pair is suppressed by decoupling capacitor at the same time. Phase noise and key parameters influencing phase noise are analyzed in detail. To guide the design, simple way to get optimum values of key parameters is also presented. This oscillator can work at low supply voltage to reduce power consumption considerably compared to conventional selfswitched biasing. The proposed oscillator is fabricated in 0.18 lm CMOS process, and exhibits a low phase noise of -77.5 dBc/Hz (FoM = 181) and -122.8 dBc/Hz (FoM = 186) at 10 kHz and 1 MHz offset, respectively, from oscillation frequency of 2.55 GHz while dissipating 2.7 mA with 1.2 V supply voltage.

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“…Therefore, there is a demand for the improvement of linearity of the LC tank . In the linear‐tuning oscillator structure, there are many ways to implement by switching capacitor array , parallel resonator , series capacitor bank , and distributed varactor biasing . In the above references, the circuits operated in the low power consumption which reduced phase noise and increased tuning range could be mutually trade‐off.…”

Section: Introductionmentioning

confidence: 99%

Design of 5‐GHz CMOS LC VCO with dual tuning circuit

Hsu

Hung

2014

Micro & Optical Tech Letters

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In this article, a linear tuning range, low power, and low phase noise of CMOS voltage controlled oscillator (VCO) is presented. The core circuit of VCO is adopted dual‐tuning LC resonator with two transformer coupling structure. The bandwidth of the frequency range is from 4.85 to 5.84 GHz with a 18.5% tuning ratio by two tuning voltages. The phase noise of the proposed VCO is −119.3 dBc/Hz at 1 MHz offset frequency. The power consumption is 5.2 mW from 1 V supply and the KVCO exhibits the linearity with 240 MHz/V. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1356–1360, 2014

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Low phase noise and linear gain VCO using self-switched biasing

Cited by 7 publications

References 9 publications

0.5 V 5.8 GHz highly linear current-reuse voltage-controlled oscillator with back-gate tuning technique

0.5 V 5.8 GHz highly linear current-reuse voltage-controlled oscillator with back-gate tuning technique

Reduction of 1/f 3 phase noise in LC oscillator with improved self-switched biasing

Design of 5‐GHz CMOS LC VCO with dual tuning circuit

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