World's first monolithically integrated Thin-Film-Transistor (TFT) SRAM configuration circuits over 90nm 9 layers of Cu interconnect CMOS is successfully fabricated at 300mm LSI mass production line for 3-dimensional Field Programmable Gate Arrays (3D-FPGA). This novel technology built over the 9 th layer of Cu metal features aggressively scaled amorphous Si TFT having 180nm transistor gate length, 20nm gate oxide, fully silicided gate, S/D, all below 400C processing essential to not impact underlying Cu interconnects. Low temperature TFT devices show excellent NTFT/PTFT transistor I on /I off ratios over 2000/100 respectively, operate at 3.3V, E-field scalable, and are stable for SRAM configuration circuits. We believe this 3D-TFT technology is a major breakthrough innovation to overcome the conventional CMOS device shrinking limitation.Introduction Downscaling of conventional CMOS device has reached its limitations and cost to develop sub 40 nm processes has dramatically increased. To overcome the CMOS shrinking limitation, various technologies such as high-k, metal gate, stress liner, and e-SiGe etc. are applied [1] or many new concept devices are reported [2][3][4].We propose a new concept for a novel 3D-FPGA using a-Si TFT configuration SRAM ( Fig. 1) over bulk CMOS logic to reduce FPGA die area, die cost and power [5]. 3D-FPGA is for prototype & low volume production. For high volume production, the TFT layer is replaced with metal layer (Fig. 2) during fabrication, which means FPGA die converts to timing-exact ASIC die without redesign effort, lowering die cost further and improving reliability. In this paper, we present the TFT fabrication technology & TFT device characteristics built over 9 layers of Cu interconnected CMOS circuits at processing temperature below 400C.Process technology Process flow for the TFT device on LSI is shown in Fig. 3. First, underlying LSI was fabricated on 300mm-Si Toshiba standard 90nm CMOS technology. After opening via's to connect the LSI to TFT, a-Si TFT' were fabricated below 400C, which is essential to maintain the reliability of Cu metal. This constraint limits the performance of TFT devices. Fig. 4 shows a cross sectional image of 9 metal layer CMOS with TFT layer (left Fig.) and a detailed TFT transistor (right Fig.). TFT transistor channel length is 180nm, with 20nm gate dielectric formed by plasma-TEOS. Fully silicided a-Si gate electrode (FUSI gate) is formed to control the Vth and boost the transistor performance. S/D is also fully silicided for higher current and to connect to underlying CMOS. NiPt and a-Si thickness is accurately controlled to form FUSI gate and S/D. TFT transistor image is shown in Fig. 5. TFT transistor performance is enhanced by using majority carrier accumulation devices. Table-1 shows the key features for this a-Si TFT technology demonstrating the densest integration for a-Si TFT in the industry. Key features of TFT processing used Toshiba 65nm CMOS fabrication techniques.Device characterization Fig. 6 (a) shows TFT transistor characteristi...

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The proposed 2.5-GHz-band impulse transmitter technology realizes frequency-stable impulse generation against PVT variation and superior energy-per-bit operation, and it can be powered directly from a − 19.5-dBm-sensitivity RF energy harvesting circuit without any regulators that are generally essential to power RF circuits. The transmitter occupies 0.38 mm 2 in a 65nm CMOS technology. The maximum frequency difference among measured output return-loss peak of 9 chips with 3 different process corners under 0.5 V supply is about 50 MHz without any frequency calibration. Our prototype achieves 1 Mb/s signal transmission under 2.3 µW power consumption from 0.5 V supply thanks to pulse-level duty cycling operation of maximally digital architecture.Index Terms -Impulse ultra-wideband radio, Ultra low power RF, RF energy harvesting I. INTRODUCTIONThe impulse ultra-wideband (I-UWB) RFID technique has been leading short-range wireless communication technology toward internet-of-things application due to its abilities of high throughput, low power consumption and so on. While previous works have realized complicating I-UWB transceivers [1], [2], one of the next significant challenges for the short-range tag technology is how to minimize the cost for expanding its application especially toward low-end and large-volume markets.This paper proposes 2.5-GHz-band impulse transmitter (TX) technology which can contribute to save a tag cost in term of power supply and form factor. Features of our approaches are (1) frequency-stable impulse generation technique, and (2) pulse-level duty cycling with suppressed leakage by maximally digital architecture. The proposed technique can generate an impulse signal with stable RF carrier-frequency against PVT variation, which enables to remove supply-voltage conditioning circuits such as regulators and to be powered by a proposed RF energy harvesting circuit (RF-EH) directly. This paper also addresses ideas to achieve both ultra-low power consumption and superior energy per bit concurrently.

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