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This paper presents a high full well capacity (FWC) CMOS image sensor (CIS) for space applications. The proposed pixel design effectively increases the FWC without inducing overflow of photo-generated charge in a limited pixel area. An MOS capacitor is integrated in a pixel and accumulated charges in a photodiode are transferred to the in-pixel capacitor multiple times depending on the maximum incident light intensity. In addition, the modulation transfer function (MTF) and radiation damage effect on the pixel, which are especially important for space applications, are studied and analyzed through fabrication of the CIS. The CIS was fabricated using a 0.11 μm 1-poly 4-metal CIS process to demonstrate the proposed techniques and pixel design. A measured FWC of 103,448 electrons and MTF improvement of 300% are achieved with 6.5 μm pixel pitch.

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An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.Keywords: Pipeline ADC, Calibration, Capacitor error-averaging, Spurious free dynamic range(SFDR), Signal to noise and distortion ratio(SNDR), Effective number of bit(ENOB).

Abstract:Coupling with a ring of capacitors introduces in-phase coupling current in multi-stage LC oscillators, increasing coupling strength and phase spacing accuracy. Capacitive coupling is effective at high-frequency applications because it increases coupling strength with the operating frequency. However, capacitive loading from the ring lowers operating frequency and reduces the tuning range. Mathematical expressions of phase noise and phase spacing accuracy with capacitive coupling are examined here, and transistor-level simulations confirm the effectiveness of the capacitive coupling.