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A 20-MHz to 3-GHz wide-range multiphase delaylocked loop (DLL) has been realized in 90-nm CMOS technology. The proposed delay cell extends the operation frequency range. A scaling circuit is adopted to lower the large delay gain when the frequency of the input clock is low. The core area of this DLL is 0.005 mm 2 . The measured power consumption values are 0.4 and 3.6 mW for input clocks of 20 MHz and 3 GHz, respectively. The measured peak-to-peak and root-mean-square jitters are 2.3 and 16 ps at 3 GHz, respectively.Index Terms-Delay cell, delay-locked loop (DLL), multiphase, wide range.

In this paper, a backstepping adaptive iterative learning control (AILC) is proposed for robotic systems with repetitive tasks. The AILC is designed to approximate unknown certainty equivalent controller. Finally, we apply a Lyapunov like analysis to show that all adjustable parameters and the internal signals remain bounded for all iterations.

A 15GHz~20GHz delay-locked loop (DLL) has been fabricated in 90nm CMOS technology. It not only relaxes the speed requirement of the voltage-controlled delay line (VCDL), but also allows the VCDL not to operate at the highest frequency. When this DLL operates at 20GHz, the measured root-mean-square and peak-to-peak jitters are 0.813ps and 6.62ps, respectively. The core area is 0.25x0.4 mm 2 and the power consumption is 49mW for 0.9V supply. INTRODUCTIONI.