A 1 V Phase Locked Loop with Leakage Compensation in 0.13  m CMOS Technology

Chuang, Chi-Nan

doi:10.1093/ietele/e89-c.3.295

Cited by 11 publications

(8 citation statements)

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“…As a result o f increasing speed in digital systems, PLLs are commonly required to generate low-jitter on-chip clocks but device and supply/substrate noise affect the PLLs opera tion which may itself result in jitter (Sidiropoulos and Horowitz, 1997;Mansuri and Yang, 2002). In order to design low-jitter PLLs, for example, the work in (Chuang and Liu, 2006) proposed a compensation circuit to reduce the jitter caused by the leakage currents in a PLL. Another proposed solution involves implementing a lowpass filter at the DC control voltage input terminal o f the VCO to suppress noise component contained in the power supply (Agilent, 2000).…”

Section: Sources Of Jittermentioning

confidence: 99%

Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

Phatrapornnant

Pont

2006

IEEE Trans. Comput.

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All rights reserved INFORMATION TO ALL U SE R S The quality of this reproduction is d ep endent upon the quality of the copy submitted.In the unlikely event that the author did not sen d a com plete manuscript and there are m issing p a g es, th e se will be noted. Also, if material had to be removed, a note will indicate the deletion. AbstractThis thesis is concerned with the development o f single-processor embedded systems in which there are requirements for both low CPU energy consumption and low levels of task jitter. The focus o f the work is on ways in which dynamic voltage scaling (DVS) techniques can be incorporated in simple time-triggered scheduling algorithms in order to meet these constraints.Following a review o f previous work in this area, a presentation is made which illustrates the impact o f a naive application o f DVS in a system incorporating a timetriggered co-operative (TTC) scheduler. Novel algorithms (TTC-jDVS, TTC-jDVS2) are then introduced which more successfully integrate TTC and DVS techniques. These algorithms involve: (i) changes to system timer settings when the frequency is altered; (ii) use o f a form o f "sandwich delay" to reduce the impact o f changes to the scheduler overhead which arise as a result o f frequency changes, and (iii) execution of jitter-sensitive tasks at a fixed operating frequency.The impact o f these algorithms on both jitter and energy consumption is illustrated empirically on a representative hardware platform, using both "dummy" task sets and a more realistic case study.In designs for which low jitter is an important consideration, at least a limited degree of task pre-emption may be required. A simple time-triggered hybrid (TTH) sched uler can be used to achieve such behaviour. A novel TTH scheduling algorithm (TTH-jDVS) is presented and evaluated, again through use o f dummy task sets and a case study.The third piece o f experimental work presented in this thesis illustrates that -in situations where minimal jitter is required -hardware support is required. To illus trate the potential o f such an approach a final case study is employed.The thesis concludes by making suggestions for further work in this important area.

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Section: Sources Of Jittermentioning

confidence: 99%

Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

Phatrapornnant

Pont

2006

IEEE Trans. Comput.

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“…Since the output current of an operational amplifier or a compensated current source is limited in [3,4], it may not compensate a large leakage current. If the leakage current becomes large enough, a false locking may occur for a PLL.…”

Section: Introductionmentioning

confidence: 99%

A leakage-current-recycling phase-locked loop in 65nm CMOS technology

Lee

Tsai

Liu

2011

IEEE Asian Solid-State Circuits Conference 2011

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A leakage-current-recycling technique is presented for phase-locked loops (PLLs) in nanoscale CMOS technology. The leakage current of the PMOS capacitor in a PLL is recycled to supply the power for a voltage-controlled oscillator, a divider and a dual-mode phase-frequency detector. This PLL is fabricated in a 65nm CMOS technology. The measured peak-to-peak jitter and rms jitter of this PLL at 640MHz are 52.2ps and 9.6ps, respectively. Its power consumption is 1mW for a 1.2V supply voltage.

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“…One is to use an additional MOS switch between a CP and a loop filter [2] and the other is an analog compensation technique using a replica CP output, a comparator and a leakage current generator [3]. The first technique is simple to design, but the leakage current mismatch reduction ratio is only 4 because leakage current flows in the added MOS switch also.…”

Section: Introductionmentioning

confidence: 99%

“…Depending on process, voltage and temperature (PVT) variations and the CP output voltage, the PMOS leakage current sometimes can be much larger (∼100 times or more) than the NMOS leakage current and sometimes vice versa. In [3], the NMOS leakage current generator is actively sinking the excessive PMOS leakage current of the CP output. Because the PMOS and the NMOS leakage currents may have very different scales, the leakage current mismatch compensation of [3] has limited compensation range and cannot operate for all PVT variations.…”

Section: Introductionmentioning

confidence: 99%

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Charge Pump circuit with wide range digital leakage current mismatch compensator

Byun

Shim

2010

IEICE Electron. Express

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Abstract:A wide range digital leakage current mismatch compensator for a short-channel charge pump (CP) circuit is presented. Equipped with leakage current generators and leakage current mirrors, the proposed leakage current mismatch compensator can reduce the PMOS and NMOS leakage current mismatch to less than 1/10 times of its initial value for wide range of leakage current mismatches. For simulation, a CP circuit with the proposed leakage current mismatch compensator was designed in a 0.13 µm 1P8M CMOS process.

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A 1 V Phase Locked Loop with Leakage Compensation in 0.13 m CMOS Technology

Cited by 11 publications

References 0 publications

Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

A leakage-current-recycling phase-locked loop in 65nm CMOS technology

Charge Pump circuit with wide range digital leakage current mismatch compensator

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