This study presents a novel system architecture to implement silicon-on-glass (SOG) MEMS devices on Si-glass compound substrate with embedded silicon vias. Thus, the 3D integration of MEMS devices can be accomplished by means of through-wafer silicon vias. The silicon vias connecting to the pads of devices are embedded inside the Pyrex glass. Parasitic capacitance for both vias and microstructures is decreased and mismatch of coefficient of thermal expansion (CTE) is reduced. In applications, the glass reflow process together with the SOG micromachining processes were employed to implement the presented concept. Successful driving of the resonator through the silicon vias is demonstrated. The wafer-level hermetic packaging can be further achieved by anodic bonding of a Pyrex7740 wafer. Hermeticity of the packaged device performed by helium leak test satisfied MIL-STD-883E. The packaged SOG device is SMT (surface mount technology) compatible and ready for 3D microsystem integration.

This study demonstrates the torque-enhancement design for a 2-axis magnetostatic SOI scanner driven by a double-side electroplating ferromagnetic film. The present design has two merits: (1) the slender ferromagnetic material patterns with higher length-to-width ratio enhance the magnetization, (2) the backside electroplating of the ferromagnetic film increases the volume of the ferromagnetic materials. This study also establishes the fabrication processes to implement the proposed design. The processes also have two merits: (1) the handle-layer of the SOI wafer is exploited as the shadow mask to pattern the seed-layer at the backside of the device layer, (2) the device layer of the SOI wafer acts as the cathode to enable simultaneous double-side electroplating. In applications, a 2-axis SOI scanner was implemented and characterized. Measurements show a 149% torque enhancement from the double-side electroplating design. The vertical slender ferromagnetic material patterns further increase the magnetostatic torque to 211%. This study also successfully demonstrates the Lissajous scanning using the presented 2-axis SOI scanner.

This study presents a novel capacitive-type Z-axis (out-of-plane) accelerometer implemented on an SOI wafer. This accelerometer contains special designed gap-closing differential sensing electrodes. The present Z-axis accelerometer has four merits: (1) mass of the proof mass is increased by combining both device and handle silicon layers of the SOI wafer, (2) the sensitivity is improved by the gap-closing differential electrodes design, (3) the electrical interconnection between the device and handle silicon layers of the SOI wafer is available by means of the metal-vias, and (4) the sensing gap thickness is precisely defined by the buried-oxide layer of the SOI wafer. In application, the Z-axis accelerometer is fabricated and characterized. Typical measurement results demonstrate that the presented Z-axis accelerometer has a sensitivity of 196.3 mV G −1 (42.5 fF G −1) and a maximum nonlinearity of 2% over the range of 0.1-1 G.

This study presents a novel dual-axis capacitive-type accelerometer design consists of a pendulum-proofmass (bulk Si), a gimbal-spring (poly-Si film), and vertical-combs sensing electrodes. This design has three merits, (1) pendulum-proofmass to produce torque by in-plane acceleration (offset-axis inertial force), (2) gimbal-springs enable the detection of dual-axis accelerations, and (3) high-aspect-ratio-micromachined (HARM) vertical-combs as the differential sensing electrodes to detect angular motion. In short, applying the HARM vertical-combs for differential capacitive sensing to detect the offset-axis inertial force is firstly implemented in this work. Measurement results show that sensitivities (non-linearity) of etch direction are 2.44mV/G (0.04%) of X-axis, and 51.99mV/G (0.11%) of Y-axis (measurement range: 0.05G~2G). The resolution is 50mG for both axes. The cross-axis errors range from 0.005% to 11%.

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