As the device dimension continues to shrink with technology development, the need for a thinner barrier for copper has risen in order to meet the requirements for finre device performance. The conventional barrier process by Physical Vapor Deposition (PVD) has the limitation to achieve conformal step coverage across the dual damascene structure [ 11, and therefore would face a bottleneck when the thickness reduction is required. In this work, the Atomic Layer Deposition (ALD) technique is applied for the TaN barrier process of a 90nm generation copper dual damascene integration with low-k dielectrics of k=3.0. The ALD technique could not only provide a conformal step coverage on both trenches and vias [2-4], it could also allows reasonable thickness control for thickness in the order of lOA. The integration results show that ALD TaN has promising electrical performance on sheet resistance, via resistance, and line-to-line leakage, and it also has superior reliability performance on electromigration, stress migration, and bias temperature test as compared with conventional PVD TaN. The ALD TaN technique is shown to provide a robust barrier process for next generation devices.

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