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This study mainly investigates the impact of high speed digital modules' radiated EMI noise on receiving performance of wireless mobile device via built-in antenna coupling. We began with designing dipole and loop antenna to represent the routing and trace pattern for common-and differential-mode current flowing inside digital modules installed in mobile devices(such as Tablet, Notebook computers, and smart phones), and then observed the coupling effect of their EMI noise on receiving antenna ports. Utilization of EMI measuring equipment described in this paper not only can obtain the interference power corresponding to the frequencies and levels of noise from device under test (DUT), we can also derive the radiation patterns related to common-and differential-mode radiation from surface scanning results. We would then further establish the relationship between the DUT characteristics and noise locations to find the optimal placement for noisy DUT and antennas. The result of this study can help to establish the preliminary noise budget for those components built in the wireless communication platforms.

This paper presents a low-power VLSI implementation of a 4-channel independent component analysis (ICA) processor for portable EEG signal processing applications. The low-power scheme employed for this ICA chip is based on power gating and clock gating by utilizing Cadence common power flow (CPF) low-power methodology and also according to the characteristics of ICA training behavior using different training window sizes. The proposed low power ICA processor can separate EEG and mixed EEG-like super-Gaussian signals in real time. The chip can be operated at up to 60MHz working frequency and a maximum sampling rate of 9.394 KHz for EEG signals. The power consumption of this chip is 0.690 mW during training under the condition of 0.9V supply voltage and 10 MHz operating frequency using UMC 90nm High-Vt CMOS technology. The total chip area is 1230 x 1230 2 m μ .I.

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