This paper proposes a modified predictive direct torque control (MPDTC) application-specific integrated circuit (ASIC) with multistage hysteresis and fuzzy controller to address the ripple problem of hysteresis controllers and to have a low power consumption chip. The proposed MPDTC ASIC calculates the stator’s magnetic flux and torque by detecting three-phase currents, three-phase voltages, and the rotor speed. Moreover, it eliminates large ripples in the torque and flux by passing through the modified discrete multiple-voltage vector (MDMVV), and four voltage vectors were obtained on the basis of the calculated flux and torque in a cycle. In addition, the speed error was converted into a torque command by using the fuzzy PID controller, and rounding-off calculation was employed to decrease the calculation error of the composite flux. The proposed MDMVV switching table provides 294 combined voltage vectors to the following inverter. The proposed MPDTC scheme generates four voltage vectors in a cycle that can quickly achieve DTC function. The Verilog hardware description language (HDL) was used to implement the hardware architecture, and an ASIC was fabricated with a TSMC 0.18 μm 1P6M CMOS process by using a cell-based design method. Measurement results revealed that the proposed MPDTC ASIC performed with operating frequency, sampling rate, and dead time of 10 MHz, 100 kS/s, and 100 ns, respectively, at a supply voltage of 1.8 V. The power consumption and chip area of the circuit were 2.457 mW and 1.193 mm × 1.190 mm, respectively. The proposed MPDTC ASIC occupied a smaller chip area and exhibited a lower power consumption than the conventional DTC system did in the adopted FPGA development board. The robustness and convenience of the proposed MPDTC ASIC are especially advantageous.

This study developed a predictive direct torque control (PDTC) application-specific integrated circuit (ASIC) with a fuzzy proportional-integral-derivative (PID) controller and a new round-off calculation circuit for improving the ripple response of a hysteresis controller when sampling and calculating delay times in an induction motor drive. The proposed PDTC ASIC not only calculates the stator's magnetic flux and torque by detecting three-phase currents, three-phase voltages, and rotor speed but also eliminates large ripples in the torque and flux by using the fuzzy PID controller. Furthermore, the proposed round-off algorithm reduces the calculation error of the composite flux. A fuzzy voltage vector switching table is proposed not only to speed up the calculating speed but also to resolve the instability generated by its large torque and flux ripples. The Verilog hardware description language was used to implement the hardware architecture, and the aforementioned ASIC was fabricated using the 0.18-μm 1P6M CMOS process of the TSMC by employing the cell-based design method. The predictive calculations, fuzzy PID controller, fuzzy voltage vector switching table, and round-off calculation algorithm improved not only the ripple issue faced in traditional direct torque control but also the control stability and robustness. The measurement results indicate that the proposed PDTC ASIC has an operating frequency, a sampling rate, and a dead time of 50 MHz, 100 kS/s, and 100 ns, respectively, at a supply voltage of 1.8 V. The power consumption and chip area of this ASIC are 1.0027 mW and 1.169 × 1.168 mm 2 , respectively. The main advantages of the proposed PDTC ASIC are its low power consumption, small chip area, robustness, and convenience.INDEX TERMS Direct torque control (DTC), Predictive calculation, fuzzy PID controller, round-off algorithm, application-specific integrated circuit (ASIC), induction motor (IM), hardware description language (HDL).

In this paper, we present a successive approximation register (SAR) analog-to-digital converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped switch, also called PLL-SAR ADC. To meet system-on-chip (SOC) and industrial requirements, the proposed SAR ADC and the control circuits of electric vehicles must be integrated into a single chip and be fabricated using the TSMC 0.25-μm 1P3M complementary metal oxide semiconductor (CMOS) high-voltage process. It is difficult to implement a high-speed SAR ADC with the TSMC 0.25-μm CMOS high-voltage process because it includes an N-type buried layer, which shorts all p-type metal oxide semiconductor field-effect transistor (PMOSFET) bodies together to withstand high voltages. In the proposed PLL-SAR ADC, two clock signals, an external clock signal and an internal clock signal from the CP-PLL, are provided to guarantee that a correct clock signal is fed. This design improves the robustness of the designed system. A monotonic capacitor-switching procedure is considered to reduce power consumption. Furthermore, a bootstrapped switch was added along with a dummy switch and a dummy transistor to eliminate disturbances in the input voltages and to improve the device’s anti-noise capability. Moreover, a two-stage dynamic comparator was used to prevent kickback noise induced by the parasitic capacitors. The measurements indicate that the signal-to-noise-and-distortion ratio, effective number of bits, power consumption, and chip area are 53.82 dB, 8.65 bits, 1.256 mW, and 1.261 × 0.975 mm2, respectively. The FoM is approximately 0.625 pJ/conv-step at 1.256 mW, 8.65 bits, and 5 MS/s. The high sampling rate of 5 MS/s and high accuracy of 8.65 bits are the main advantages of the proposed PLL-SAR ADC.

This paper presents a 10-bit 0.909-MHz 8-channel dual-mode successive approximation (SAR) analogue-to-digital converter (ADC) for brushless direct current (BLDC) motor drive, using a Taiwan Semiconductor Manufacturing (TSMC) 0.25 μm 1P3M Complementary Metal Oxide Semiconductor (CMOS) process. The sample-and-hold (S/H) circuit operates with two sampling modes. One is individually sampling eight channels in sequence with an S/H circuit and the other is sampling four channels simultaneously with four S/H circuits. All sampled data will be digitized with high-speed SAR ADC in time division multiplexing (TDM). A dynamic latch-type comparator is utilized to latch the output at an upper or lower level. The advantage of the designed comparator is that it performs with positive feedback to quickly complete the latch function. The double-tail latch-type architecture is utilized to mitigate the significant kickback effect by separating the pre-amplifier stage from the latch. By integrating an input NMOSFET with an input PMOSFET, the designed latch-type comparator can perform with full-swing input voltage. Measurements show that the signal-to-noise ratio (SNR), signal-to-noise-and-distortion ratio (SNDR), effective number of bits (ENOB), power consumption, and chip area are 50.56 dB, 57.03 dB, 8.11 bits, 833 μW, and 1.35 × 0.98 mm2, respectively. The main advantages of the proposed multichannel dual-mode SAR ADC are its low power consumption of 833 μW and high measured resolution of 8.11 bits.