A study on physical design of VLSI Floor planning is discussed using optimization techniques for betterment in performance of VLSI chip. Floor planning in VLSI is considered to be a Non Polynomial problem. Such problems can be solved using computations. The initial step in floor plan is the representation of floor plan design. The floor plan representations show greater impact on the search space and the complexity of the floor plan design. The objective of this paper is to study different algorithms that addressees the problem of handling alignment constraints such as good placement, optimum area and short run time. Different heuristic and meta-heuristic algorithms are proposed and suggested by many researchers for solving the VLSI Floor plan problem. In this paper Simulated Annealing algorithm, Ant Colony Algorithm, Tabu search and Genetic algorithms are discussed.

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The complexity of Application Specific Integrated Circuits (ASICs) is continuously increasing. Consequently chip-design becomes more and more challenging. To handle this complexity for a fast ASIC development, the existing design process has to become more efficient. To achieve this, we used an approach based on a multi-agent simulation. A mutli-agent system is an intuitive way to represent a team of designers, creating an ASIC. Furthermore, MAS are capable of coping with the natural dynamics of the design process, reacting to and modelling unforeseen events. The resulting Model is capable of an extensive analysis of the design process. It can make reliable predictions on design project courses and identify weak spots within the design process. It can provide status-anlysis of ongoing projects and suggestions on how to organize, plan and execute a new project efficiently.

Because of constantly improving technologies, the complexity of Integrated Circuits (ICs) is continuously increasing. Consequently IC design becomes continously more challenging and complex. A huge number of different possible design flows exists, delimited by different constraints. The design flow dynamically changes as recursions between design tasks occur. An approach that allows a fast and efficient ASIC design and that can deal with this huge complexity and dynamics is needed. Therefore we propose a methodology based on a multi-agent simulation combined with global and local scheduling techniques to construct a time-dependent, detailed model of the ASIC design process, which permits an extensive analysis and efficient organization.