Using genetic algorithms for planning of ASIC chip-design project flows

Abstract

A study on physical design of VLSI Floor planning is discussed using optimization techniques for betterment in performance of VLSI chip. Floor planning in VLSI is considered to be a Non Polynomial problem. Such problems can be solved using computations. The initial step in floor plan is the representation of floor plan design. The floor plan representations show greater impact on the search space and the complexity of the floor plan design. The objective of this paper is to study different algorithms that addressees the problem of handling alignment constraints such as good placement, optimum area and short run time. Different heuristic and meta-heuristic algorithms are proposed and suggested by many researchers for solving the VLSI Floor plan problem. In this paper Simulated Annealing algorithm, Ant Colony Algorithm, Tabu search and Genetic algorithms are discussed.

Organizing and Planning the Asic Design Process by Means of a Multi-Agent System

“…The objective of the optimization is the minimization of the overall execution time of an ASIC design project: min T design , while tasks need to be assigned to designers with different experience modes out of different design regions and tools considering task dependencies and resource constraints. We use a scheduling optimization heuristic based on genetic algorithms (GA) (Blaschke et al, 2009). Designers planned holidays are incorporated in the optimized schedule.…”

Optimization of chip design processes using task graphs

“…Project cancellations in semiconductor companies are causing up to $ 4 billion a year of wasted R&D investment [4]. Recent approaches which try to simulate and predict chip design processes are characterized by a huge number of input parameters [5,6]. However, quick changes in technology and increasing complexity of the designs require a fast adaption of planning and performance measurement methods.…”