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As device dimensions have shrunk well below the one micron level, linewidth control particularly over reflective topography has become a major problem in optical lithography. Other than reflective notching caused by light reflected into unwanted areas, thin-film interference is the major contributor to linewidth variations. Small changes in film thickness over steps cause significant changes in the amount of energy deposited into photoresist films. Various methods used to solve this problem are investigated to measure their relative effectiveness. Conventional photoresist, dyed-resist, bottom layer ARCs (antireflective coatings; both inorganic and organic), TAR (top-antireflective layer) and CEL (contrast enhancement layer) as a special case of TAR are compared for their relative effectiveness as well as their advantages and disadvantages for use in manufacturing. Simulations and functional evaluation of film thickness effects on exposure requirement and on Iinewidths as well as imaging over topography are used as a means of comparison.'I'hc use of TAR is a relatively new approach to solving this problem in a simple, efFective manner. Material choice depends on film refractive index and ease of processing. Several TAR materials have been investigated and will be discussed.

As lithographic technology nodes advance beyond the 193nm generation, the optical absorption oforganic materials will require the use ofthin layer imaging (111) techniques. Ofthe techniques under consideration, the use ofultra-thin resist (LJTR) over a hardmask is the most desirable because of its simplicity and close similarity to standard single layer resist processes. Prior work has demonstrated that the UTR process is capable ofpattem transfer to poly silicon device layers with as little as I000A ofresist on flat wafers using 248nm lithography. This was achieved with defect levels comparable to a conventional 5000A resist process. In this work, we demonstrate "proof of concept" by integrating the UTR process into the transistor gate module of a production device using 248nm lithography. In doing so we focus on three key areas for manufacturability: inherent defectivity ofUTR films, sensitivity ofthin resist to topography, and quality ofpattem transfer. We fmd that pinhole defects are oflittle concern in the UTR process after SEM review of defects on un-patterned UTR films. We show that the UTR process is sensitive to wafer topography, since it does not provide a completely planar surface over the underlying device features. Finally, we demonstrate that the UTR process is capable ofreliable pattern transfer on a production device with defect levels comparable to the thicker baseline single layer resist process.

Thin film interference plays a destructive role in optical photolithography in two regards. (1) Large linewidth variations can occur from tiny changes in the thickness of resist or underlying thin films. (2) Asymmetric flow of resist over alignment mark topography can cause optical fringes which result in poor alignment signal profiles. In this paper, a new approach is described which can address both of these issues. A thin, low index, transparent film analogous to a lens antirefiector (AR) coat is placed on top of the photoresist film before exposure. The ideal top antireflector (TAR) film would have thickness T = A / (4n') and n' = ~n where nand n' are the refractive indices of resist and TAR, respectively. Experimental results are presented which show how various TAR layers can improve linewidth control and reduce notching as lines are patterned over topographic steps. In addition, simulations are presented which demonstrate how a TAR layer can improve the alignment signal, for certain types of alignment systems. The TAR process has great potential for high volume, economical semiconductor manufacturing.

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