No abstract

No abstract

This paper presents a testing method of the interconnect resource (IR) for Field programmable gate arrays (FPGAs) which takes the programmable switch boxes (SBs) as the core of faults testing and diagnosis by mapping faults to their corresponding configurable logic blocks (CLBs). CLBs in FPGA have also been employed to enhance driving capability. The proposed technology can achieve 100% test coverage of the SB faults in IRs, as well as precisely identify the fault type and locate faults. An in-house developed FPGA test system based on SOC hardware/software verification technology has been applied to test XC4000E family of Xilinx. The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns with test vectors.

A traditional bottom-up modeling method for minimum configuration numbers is adopted for the study of FPGA minimum configurations. This method is limited if a large number of LUTs and multiplexers are presented. Since graph theory has been extensively applied to circuit analysis and test, this paper focuses on the modeling FPGA configurations. In our study, an internal logic block and interconnections of an FPGA are considered as a vertex and an edge connecting two vertices in the graph, respectively. A top-down modeling method is proposed in the paper to achieve minimum configuration numbers for CLB and IOB. Based on the proposed modeling approach and exhaustive analysis, the minimum configuration numbers for CLB and IOB are five and three, respectively.