Over the past decade, boron‐doped diamond tips have become the ultimate choice for electrically characterizing microelectronics devices using scanning probe methods such as scanning spreading resistance microscopy (SSRM). Although nanometer‐scale electrical resolution has been demonstrated, the development of a reliable probe process remained a challenge. Therefore, we did develop in this work solid diamond tips with sub‐nanometer electrical resolution and integrated them into metal cantilevers using a peel‐off approach. It is shown that the ultra‐high tip resolution is achieved by diamond nanocrystals protruding from the apex of the diamond pyramid. The yield for sub‐nanometer probes is 20–30% in air and 40–60% in vacuum. This paper describes the fabrication scheme, discusses probe characterization, and shows SSRM measurements obtained with these probes. Our probes are routinely used for SSRM measurements and current efforts are focusing on increasing the yield for sub‐nanometer tips further.

No abstract

This paper focuses on the substrate transfer process which is applied after the fabrication of LEDs on 4 inch Si (111) wafers comprising p and n contact formation to the GaN layer. After applying a passivation layer, a bonding metal is deposited. The wafer is then bonded to a Si carrier substrate using metallic bonding. Next, the original Si (111) substrate is completely removed by grinding and wet etching. GaN-LEDs are thus transferred to a new carrier substrate. The last step is etching of the transferred GaN layer from the back to open the contacts. A surface roughening technique on the backside of the transferred GaN layer to improve the light extraction efficiency of GaN-LEDs is also investigated. All the issues of the substrate transfer process steps such as permanent Cu/Sn bonding, thinning by grinding and wet etching will be discussed in detailed. A typical issue occurring during processing of GaN-LEDs on Si substrates is high stress and related large wafer bow originating from the GaN layer and the thick Cu/Sn metal bonding layer. Such a large wafer bow causes problems for some automatic handling tools and processes like lithography. Solutions to manage the stress and wafer bow have been investigated.

X-ray photoelectron spectroscopy (XPS) has become increasingly important over the past few years for supporting the development of ultra-thin layers for high-k metal gates. As the analysis depth of XPS is however limited to about 5-7 nm, it would be extremely useful if the analysis could be carried out from the backside using standard silicon wafers. This approach puts extreme requirements on the sample preparation as hundreds of micrometers of bulk silicon have to be removed and one has to stop with nanometer precision when reaching the interface to the ultra-thin layer stack. Therefore, we have developed dedicated procedures for preparing and analyzing samples for backside XPS analysis. This paper presents the developed approach with a focus on sample preparation using plan-parallel polishing, endpoint detection by interference fringes, and selective wet etching. First angle-resolved XPS (ARXPS) analysis results of metal gate stacks demonstrate the power of such backside analysis.

No abstract