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A VHDL-AMS model of an injection locked voltage controlled oscillator is presented in this paper. The model is valid for any harmonic of the synchronization signal. Properties such as locking-range, bandwidth and settling time are taken into account. The model is used in mixed simulations to reduce the computation time. A comparison with a schematic LC oscillator shows very good correlation.

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Clock and data recovery (CDR) is the first logical block in serial data receiver and the latter performances depend on the CDR ones. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe process is presented. The CDR uses an Injection Locked Oscillator (ILO) and a feedback loop to lock the data and the clock in frequency and phase. The power consumption is 1.4 W under 2.3 V power supply.