SiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link

Béraud-Sudreau, Quentin; Bégueret, Jean-Baptiste; Mazouffre, Olivier; Pignol, M.; Baguena, L.; Neveu, Claude; Deval, Yann; Taris, Thierry

doi:10.1109/jssc.2014.2317151

Cited by 8 publications

(15 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We propose an ILCDR to enable a fast acquisition time and good jitter tolerance. Indeed, this kind of CDR has an input-jitter-ltering nature as opposed to CDRs based on high-Q lter or gated oscillator [7,10].…”

Section: Cdr Architecturesmentioning

confidence: 99%

See 1 more Smart Citation

A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

Mao

Charlon

Jacquemod

et al. 2022

Preprint

View full text Add to dashboard Cite

In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using 28 nm FDSOI technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors allows us to create a QRO (Quadrature Ring Oscillator) reducing both size and power consumption. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we can propose a low power ILCDR with low jitter and fast locking time for burst-mode applications. The main novelty consists in the implementation of a complementary QRO based on back-gate control using FDSOI technology in order to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (27 PRBS) at 868Mbps, the recovered clock jitter is 18.5 ps (1.6%UIp-p) and the recovered data jitter is 18.7 ps (1.6%UIp-p). With a 0.6 V power supply, the power consumption is 4.67 mA (2.8 mW). The estimated Chip size is around 6600 µm².

show abstract

Section: Cdr Architecturesmentioning

confidence: 99%

“…These closed-loop architectures are the most used essentially for their low jitter [1,2,5,6]. The second ones are open loop structures with low power, fast locking time, simple and low-cost design [7].…”

Section: Cdr Architecturesmentioning

confidence: 99%

A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

Mao

Charlon

Jacquemod

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…While 50 GHz spacing can be readily achieved in the transmitter, there are several challenges in terms of the receiver, the most critical of which are available filtering techniques to accurately analyze the performance of the channel under test. At 1550 nm, injection locking was shown to improve filtering [25] for data recovery [26] and to increase BW [27]. At 2000 nm, injection locking was shown to narrow the linewidth of lasers to permit higher-order modulation formats [17].…”

Section: B Injection Locking At 2000 Nm-a Path To Filteringmentioning

confidence: 99%

Key enabling technologies for optical communications at 2000 nm

et al. 2018

View full text Add to dashboard Cite

“…Moreover, it has permitted the integration of high-bit-rate communication systems [1] and enabled the opportunity for fully integrated solutions of new wireless communication standards for millimeter-wave radio links [2]. Thanks to the advancements in complementary metal-oxide-semiconductor and BiCMOS process technology, the operating frequency of metal-oxide-semiconductor and bipolar transistors has scaled to the millimeter-wave range allowing the miniaturization of radar and imaging systems operating at these frequencies.…”

Section: Introductionmentioning

confidence: 99%

“…Thanks to the advancements in complementary metal-oxide-semiconductor and BiCMOS process technology, the operating frequency of metal-oxide-semiconductor and bipolar transistors has scaled to the millimeter-wave range allowing the miniaturization of radar and imaging systems operating at these frequencies. Moreover, it has permitted the integration of high-bit-rate communication systems [1] and enabled the opportunity for fully integrated solutions of new wireless communication standards for millimeter-wave radio links [2]. In these types of systems, the phase noise capabilities of the local oscillator are quite challenging.…”

Section: Introductionmentioning

confidence: 99%

Analysis and design of LC oscillators associated with frequency multipliers: a phase noise perspective

Cabrera

Bégueret

Mazouffre

et al. 2017

Circuit Theory & Apps

View full text Add to dashboard Cite

When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1∕f 2 phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence on the oscillating frequency in the transition from two different regimes, named the inductor-limited quality factor and the capacitor-limited quality factor. The results obtained enable the evaluation of the phase noise performance of systems based on a sub-harmonic and super-harmonic oscillators and how they compare with an oscillator in the fundamental mode. Crucial questions like the phase noise improvement that these systems can achieve are analytically answered. A design methodology is thus proposed and verified through measurements on a frequency source at 31 GHz, composed by a sub-harmonic voltage-controlled oscillator followed by an injection-locked frequency tripler, dedicated to backhauling applications, designed on a BiCMOS process technology. The tuning range is 10%, and the phase noise at a 1-MHz offset is −112 dBc/Hz. D. CABRERA, ET AL. ¶ While Q L increases with the frequency, Q C decreases asymptotically. ‖ Note that the phase noise is an increasing function even when the resonator quality factor increases with frequency. Figure 9. Improvement in the phase noise at 1-MHz offset by using a system composed of a sub-harmonic oscillator and an ideal frequency multiplier-by-n over a fundamental oscillator at 31 GHz.A simplified view of the gm cell used in [5] for the VCO is presented in Figure 12. A DC-decoupling network composed of C f and r f is used to allow a differential amplitude of 1.4 V while keeping at 0 V the maximum forward voltage of the base-collector junction of each transistor, hence keeping the transistors out of the saturation region. The bias voltage is Vb1 = 995 mV. Considering the signal magnitudes involved in the cross-coupled pair and its voltage/currentdependent capacitances, a large signal analysis should be followed to determine G ; however, an

show abstract

SiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link

Cited by 8 publications

References 13 publications

A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

Key enabling technologies for optical communications at 2000 nm

Analysis and design of LC oscillators associated with frequency multipliers: a phase noise perspective

Contact Info

Product

Resources

About