This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode.

This paper presents the design and post-layout simulation of a two-stage operational amplifier (opamp) with Miller compensation. The TSMC 0.18µm PDK was used for the design, simulation and implementation in Cadence Virtuoso. The opamp exhibits 20µW power consumption with a 1-V rail-to-rail supply. Post layout simulation shows a unity gain bandwidth (UGBW) of 69.18 MHz (Av = 49.63dB) with a phase margin (PM) larger than 86°and a Slew rate of 19.87µV/s making our design suitable for small and large signal applications.