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With increasing demands on design and optimization of analog circuits in real applications, a limited number of algorithms for practical use have been presented. The drawbacks of already existing standard algorithms are in a possibility to stagnate in a not optimal solution and also big time consumption. These drawbacks have been overcome by our new proposed algorithm STOHE. The new algorithm is a combination of a STOchastic and HEuristic algorithms. As the stochastic respectively heuristic algorithm was chosen differential evolution algorithm respectively simplex algorithm. The algorithm has been verified by the design and optimization of an active OTA-C filter where the standard approach fails.

At this moment in the field of FPGA, only RAM tests have been carried out to evaluate its performance but these works have not focused on tracking memory usage in real time, this paper proposes a design for monitoring the memory of an embedded system, in the logical part, making use of the communication between the FPGA and the HPS. In addition, the HPS has implemented a web service that allows to visualize a graph of the monitoring in real time. The proposed design can be an introduction to the development of applications that can be specifically monitored for a component of the embedded system in FPGA, because FPGA is currently being used for different purposes such as machine learning, real-time image processing, mining of Bitcoins, among others. These applications are quite robust, which implies a high demand for processing for the embedded system.

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This article describes waffle power MOSFET segmentation and defines its analytic models. Although waffle gate pattern is well-known architecture for effective channel scaling without requirements on process modification, until today no precise model considering segmentation of MOSFETs with waffle gate patterns, due to bulk connections, has been proposed. Two different MOSFET topologies with gate waffle patterns have been investigated and compared with the same on-resistance of a standard MOSFET with finger gate pattern. The first one with diagonal metal interconnections allows reaching more than 40% area reduction. The second MOSFET with the simpler orthogonal metal interconnections allows saving more than 20% area. Moreover, new models defining conditions where segmented power MOSFETs with waffle gate patterns occupy less area than the standard MOSFET with finger gate pattern, have been introduced.