No abstract

A new device interconnect scheme for sub-micron VLSI has been developed. In this technology N+ and P+ diffusions and N+ and P+ gates of a CMOS process can be directly connected in any combination desired without the use of contacts or aluminum. This provides much improved packing density over conventional processes. Since the source/drain (S/D) contacts can extend over the field oxide regions, minimum sized S/D diffusion areas can be used. This leads to a significant decrease in parasitic diffusion capacitances relative to other processes. Several. devices can share one contact when they need to communicate, and so the total number of contacts can be greatly reduced. Since the contacts do not have to be limited to minimum dimensions a relaxation of sub-micron contact processing is achieved. In addition the use of a self-aligned silicide reduces interconnect and other device parasitic resistances. NMOS and PMOS devices have been successfully fabricated using this process.

properties of shallow n+ and p t junctions (0.17-0.20 um) in Si.We have examined the impact of TiSi2 formation on the The deposited Ti thickness was varied from 300A to 1000A. The p+ junctions developed high leakage currents after reaction junctions were not degraded. In these studies LOCOS isolation with Ti of initial thickness greater than 700A while the n+ was used and the TiSi2 was formed away from the island edges. Additional experiments were performed on n+ diodes using SWAMI isolation with the TiSi2 formed right upto the edges rlf the isolation. From step-height, spreadln resistance and RDS measurements it was found that the tzickness of TiSi2 formed on n+ Si was less than on p+ Si for a given initial Ti thickness. The amount of electrically active dopant remaining in the substrates was seen to decrease with increasing Ti thickness. This was supported by SIMS measurements which also showed an accumulation of atomic fluorine at the TiSi2 interface. Cross-sectional transmission electron microscopy was used to examine the silicide morphology and interface planarity.

The phenomenon of enhanced flow of phosphosilicate glass (PSG) by ion implantation is reported here. By implanting As into PSG, excellent reflow has been obtained in inert ambients at temperatures as low as 750C. Sensitivity of reflow to percentage of oxygen (in nitrogen ambient) as well as to the energy of the As ions has been investigated. For thecase of B, BF2, F, Ar, Se, and Sb implants, no similar reflow has been observed. CV and conduction experiments have shown the dielectric integrity to be unaffected by the implant. RBS depth profiling and resistivity measurements show As redistribution with no penetration to the substrate. This technology has been implemented into a VLSI process.