The uid Generalized Processor Sharing GPS algorithm has desirable properties for integrated services networks and many P acket Fair Queueing PFQ algorithms have been proposed to approximate GPS. However, there have been few high speed implementations of PFQ algorithms that can support a large number of sessions with diverse rate requirements and at the same time maintain all the important properties of GPS. The implementation cost of a PFQ algorithm is determined by 1 computation of the system virtual time function and 2 maintaining the relative ordering of the packets via their timestamps scheduling; and 3 in some algorithms, regulation of packets based on eligibility times. While most of the recently proposed PFQ algorithms reduce the complexity of computing the system virtual time function, the complexity o f s c heduling and tra c regulation and therefore the overall complexity o f implementing PFQ, is still a function of the number of active sessions. In addition, while reducing the algorithmic or asymptotic complexity has been the focus of most analysis, it is also important t o reduce the complexity of basic operations in order for the algorithm to run at high speed. In this paper, we develop techniques to reduce both types of complexities for networks of both xed and variable size packets. In our approach, regulation and scheduling are implemented in an integrated architecture that can be viewed as logically performing sorting in two dimensions simultaneously. By using a novel grouping architecture, we are able to perform this with an algorithmic complexity independent of the number of sessions in the system at the cost of a small controllable amount of relative error. To reduce the cost of basic operations, we propose a hardware implementation framework and several novel techniques that reduce the on-chip memory size, o-chip memory bandwidth, and o-chip access latency. The proposed implementation techniques have been incorporated into commercial ATM switch and IP router products.
Abstract-To support the Internet's explosive growth and expansion into a true integrated services network, there is a need for cost-effective switching technologies that can simultaneously provide high capacity switching and advanced QoS. Unfortunately, these two goals are largely believed to be contradictory in nature. To support QoS, sophisticated packet scheduling algorithms, such as Fair Queueing, are needed to manage queueing points. However, the bulk of current research in packet scheduling algorithms assumes an output buffered switch architecture, whereas most high performance switches (both commercial and research) are input buffered. While output buffered systems may have the desired quality of service, they lack the necessary scalability. Input buffered systems, while scalable, lack the necessary quality of service features. In this paper, we propose the construction of switching systems that are both input and output buffered, with the scalability of input buffered switches and the robust quality of service of output buffered switches. We call the resulting architecture Distributed Packet Fair Queueing (D-PFQ) as it enables physically dispersed line cards to provide service that closely approximates an output-buffered switch with Fair Queueing. By equalizing the growth of the virtual time functions across the switch system, most of the PFQ algorithms in the literature can be properly defined for distributed operation. We present our system using a crossbar for the switch core, as they are widely used in commercial products and enable the clearest presentation of our architecture. Buffering techniques are used to enhance the system's latency tolerance, which enables the use of pipelining and variable packet sizes internally. Our system is truly distributed in that there is neither a central arbiter nor any global synchronization. Simulation results are presented to evaluate the delay and bandwidth sharing properties of the proposed D-PFQ system.
While PFQ algorithms can provide per-flow end-to-end delay guarantees for real-time traffic or protection among competing best-effort traffic, they have two important limitations. The first one is that, since only one parameter (a weight) is used to allocate resource for each flow, there is a coupling between delay and bandwidth allocation. When used for real-time traffic, this can result in network under-utilization. The second and less well known limitation is that, when used for best-effort traffic, PFQ algorithms favor throughputoriented applications such as FTP over delay-sensitive bursty applications such as WWW, and telnet. This is due to the memory-less instantaneous fairness property of PFQ algorithms. In a previous study [1], we proposed the Fair Service Curve (FSC) algorithm which enables more flexible delay and bandwidth allocation for real-time traffic through the use of non-linear service curves. In this paper, we show that, when used for best-effort traffic, FSC can improve performance of delay-sensitive bursty applications without negatively affecting the performance of throughput-oriented applications.
While PFQ algorithms can provide per-flow end-to-end delay guarantees for real-time traffic or protection among competing best-effort traffic, they have two important limitations. The first one is that, since only one parameter (a weight) is used to allocate resource for each flow, there is a coupling between delay and bandwidth allocation. When used for real-time traffic, this can result in network under-utilization. The second and less well known limitation is that, when used for best-effort traffic, PFQ algorithms favor throughputoriented applications such as FTP over delay-sensitive bursty applications such as WWW, and telnet. This is due to the memory-less instantaneous fairness property of PFQ algorithms. In a previous study [1], we proposed the Fair Service Curve (FSC) algorithm which enables more flexible delay and bandwidth allocation for real-time traffic through the use of non-linear service curves. In this paper, we show that, when used for best-effort traffic, FSC can improve performance of delay-sensitive bursty applications without negatively affecting the performance of throughput-oriented applications.
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