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Previously, in derailed characterization of the NMOS cryogenic hot-carrier failure mode, major deviations from room temperature behavior were found. However, to date, no similar detailed analysis of the PMOS cryogenic hotcarrier effect has been performed. The purpose of this work is to investigate the PMOS hot carrier effect at cryogenic temperatures. One of our primary findings shows that PMOS devices aged at low temperatures can undergo a drastic rebound-like effect that results in distinct reduction in device drive and large threshold voltage shift. PMOS degradation of this degree is not observed for room temperatm hot-carrier aging. Charge pumping measurements are used to measure the different behaviors with 77K and 300K hot-carrier stressing. Although the initial damage appears similar (same gm increase and Vt shift with stress time), subsequent annealing indicates that the damage mechanism at 77K differs markedly from that at 300K. Low temperature stressing initially induces the typical room temperature gm increase due to channel length shortening caused by trapped electrons. However, low-temperature stressing also appears to induce hole generation and substantial interface state creation unlike 300K stressed devices. This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures.

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