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The Direct Sequence Spread Spectrum (DSSS) communication system is widely used in ground to air missile links due to its anti-jam and low Signal to Noise Ratio (SNR) requirement advantages. The paper presents the challenges in achieving fast signal acquisition in this scenario and brings out the implementation challenges for achieving simultaneous Doppler estimation and phase delay of Pseudo Noise (PN) code. A new scheme for PN code phase delay estimation with correlation of differential signals, followed by precise Doppler estimation using Fast Fourier Transform (FFT) is presented. The area optimized Field Programmable Gate Array (FPGA) friendly architecture is utilized for rapid signal acquisition by combining both time and frequency domain approaches. The advanced design practices inFPGAs are used to achieve resource sharing and high clock speed of operation. The architecture is synthesized for Virtex-6 LX240T FPGA, resulting in 52% of area occupancy and 134 MHz of maximum allowed clock frequency value.

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In this paper, a new approach to design VLSI architecture for DSSS is proposed and implemented. In this we aimed towards designing a low power and low complexity architecture. An extremely lucid technique is implemented in Generating the Pseudo Random Sequence, which is the principal component in the design. The various blocks of the design like encoder, decoder, linear feedback shift register etc., are realized using low power VLSI components with an ease of low complexity approach. The Design is implemented on XA9536XL CPLD using XILINX ISE simulator and XILINX XST synthesizer. The results reveal that the power consumption, number of slice registers and other combinational circuits are less compared to the existing architectures.

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