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We demonstrate an additive ink-jet process to fabricate homogeneous CdS semiconductor films for thin film transistors (TFTs). This process combines in-situ synthesis with ink-jet printing at a maximum processing temperature of 250 • C. The solvent in the reaction is used to dissolve the cadmium and sulfur precursors. The reaction to form the CdS films takes place in a solid-state mode. This method does not require preliminary nanoparticles synthesis or organic stabilizers and results in film with near zero precursor waste. TFTs with mobilities of 7.5 × 10 −2 cm 2 /V · s, threshold voltage (V T ) of 3.4 V and on/off current ratio of 8 × 10 4 were demonstrated.Printed electronics have become a promising technology for flexible electronics. Besides the inexpensive aspect of Inkjet printing, additional advantages include the ability to deposit a wide range of materials, as well as low material wastage. 1-6 Currently, most inkjetprinted semiconductors for flexible electronics are organic, which typically have poor performance with mobilities around 0.1-1 cm 2 /V · s. Stability is also a potential issue for organic materials since its poor air and moisture stability compromise device reliability. 7 On the other hand, inorganic materials, in particular chalcogenide nanoparticles, have attracted the attention because these materials can be solutionprocessed and are chemically stable upon exposure to air. 8 Recently, several authors have reported cadmium sulfide (CdS) semiconductor films and other inorganic layers using printed nanoparticles to demonstrate TFTs. 9-12 Nevertheless, inorganic inks require the synthesis of nanoparticles with tight particle size control and further stabilization to eliminate aggregation and precipitation. One way to eliminate this issue is to use organic stabilizers. However, such stabilizers could act as insulating layers and hinder efficient carrier transport with the concomitant poor electrical performance. 13 In addition, subsequent high temperature annealing processes are necessary to eliminate the organic binders and to further sinter the nanoparticles. This annealing can also result in film cracking and peeling-off. 6 In this letter, we report an inexpensive and low material wastage additive method to grow CdS thin-films for active layer in TFTs. This is an easy and simple process that combines merits of in-situ synthesis where the reaction happens directly at the interface with the substrate (dielectric in this case). Ink-jet printing is used to selectively deposit the material in the desired area and to eliminate further patterning. ExperimentalThe ink was prepared with cadmium acetate dihydrate (Cd(CH 3 COO) 2 · 2H 2 O) [0.1 M] and thiourea (CH 4 N 2 S) [0.2 M] mixed in methanol/ethylene glycol (ratio 95:05). TFTs were fabricated using bottom-gate top-contact architecture. To fabricate the TFTs, 500 nm of SiO 2 were thermally grown on a Si wafer as buffer layer. Then, 5 nm of chrome followed by 100 nm of gold were deposited by E-beam evaporation and patterned to form the gate contac...

We report the fabrication and device analysis to enable high performance/low-temperature complementary thinfilm transistors (CTFTs) with 6, 13-Bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) and cadmium sulfide (CdS). Isolated transistors are first studied and then integrated in a fully patterned CTFT structure. N-type TFTs were fabricated using atomic layer deposition HfO 2 as gate dielectric, followed by a CdS film deposited by chemical bath deposition at 70°C. A novel approach that uses a parylene-C hard mask to avoid damage to the CdS n-type semiconductor is introduced. Also, a comparison between the n-type transistor performance using two different metals (Au and Al) for source-drain electrodes is presented. P-type transistors were fabricated using a novel approach that combines photolithography and ink-jet printing processes. TIPS-pentacene is deposited with inkjet printing in the active channel well, which is photolithographically defined. The p-type TFT mobilities ranged from 1.2 × 10 −3 to 1.5 × 10 −2 cm 2 /V-s, whereas for n-type TFTs mobilities were ∼10 cm 2 /V-s. CTFTs with a maximum processing temperature of 150°C are demonstrated. Inverters with gains of 17 were achieved. This fabrication process is compatible with large area and low-cost technologies for flexible electronics applications.