Enabling Hybrid Complementary-TFTs With Inkjet Printed TIPS-Pentacene and Chemical Bath Deposited CdS

Abstract

We report the fabrication and device analysis to enable high performance/low-temperature complementary thinfilm transistors (CTFTs) with 6, 13-Bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) and cadmium sulfide (CdS). Isolated transistors are first studied and then integrated in a fully patterned CTFT structure. N-type TFTs were fabricated using atomic layer deposition HfO 2 as gate dielectric, followed by a CdS film deposited by chemical bath deposition at 70°C. A novel approach that uses a parylene-C hard mask to avoid damage to the CdS n-type semiconductor is introduced. Also, a comparison between the n-type transistor performance using two different metals (Au and Al) for source-drain electrodes is presented. P-type transistors were fabricated using a novel approach that combines photolithography and ink-jet printing processes. TIPS-pentacene is deposited with inkjet printing in the active channel well, which is photolithographically defined. The p-type TFT mobilities ranged from 1.2 × 10 −3 to 1.5 × 10 −2 cm 2 /V-s, whereas for n-type TFTs mobilities were ∼10 cm 2 /V-s. CTFTs with a maximum processing temperature of 150°C are demonstrated. Inverters with gains of 17 were achieved. This fabrication process is compatible with large area and low-cost technologies for flexible electronics applications.

Analysing the TIPSP‐based VOFET through transistor efficiency ( g m /I D )

“…The channel length (L) has been kept at 90 nm, the smallest value for L, reported so far. TIPSP has been reported as being p-type or n-type [11][12][13][14][15][16][17][18][19][20] with operational voltage ranging between 10 and 30 V which is too high to meet today's needs of the electronics industry, particularly for mobile applications. Our emphasis is to propose the VOFETs capable of operating below −2 V, i.e.…”