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A theoretical analysis of the effects of the delay-line differential nonlinearity (DNL) on the typical performance parameters of high-resolution time-to-digital converters (TDCs) based on delay-locked-loop (DLL) delay lines has been developed. The theoretical study is based on the knowledge of the delay-line nonlinearity values that can be measured, with the desired precision, by means of a statistical code-density test. In particular, the effects on the TDC time resolution and error standard deviation curve as a function of the measured time interval are investigated. An a posteriors linearization technique, consisting in a proper correction of the TDC readouts, is then analyzed and its advantages are theoretically demonstrated. Finally, the theoretical results are superimposed on experimental data coming from a real TDC. The measured deviations from the ideal behavior are thus justified and can just be ascribed to the delay-line nonlinearity

A Digital-to-Time Converter (DTC) based on a Delay-Locked Loop (DLL) for phase interpolation in Direct Digital Synthesis (DDS) applications is described. The conversion is made in two steps using digitally controllable delay cells with configurable shunt-capacitors load. The circuit is able to interpolate a 120 MHz clock, generating a delay proportional to an 8-bit digital control word with 32 ps resolution. The DDS system clock frequency is thus virtually enhanced up to about 30 GHz, achieving a strong reduction of the spurious component level. The 256 level interpolation is achieved using only 35 delay elements (excluding dummy cells).

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