A Self-Calibrating Delay-Locked Delay Line With Shunt-Capacitor Circuit Scheme

Baronti, Federico; Lunardini, D.; Roncella, Roberto; Saletti, Roberto

doi:10.1109/jssc.2003.821773

Cited by 33 publications

(12 citation statements)

References 13 publications

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“…A shunt-capacitor circuit scheme capable of gener~tin.g.16 different delays proportional to the value of a 4-bIt dIgItal control word [11], was used for each delay-cell. We point out that this choice allows a rather small delay adjustment range if we want to keep low the delay quantization error.…”

Section: Simulation Resultsmentioning

confidence: 99%

Self-adjusting multiple-period locked delay line For high-resolution multiphase clock generation

Baronti¹,

Lunardini²,

Roncella³

et al. 2005

2005 12th IEEE International Conference on Electronics, Circuits and Systems

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We present a novel Delay-Locked Loop (DLL) based architecture for multiphase clock generation with a time resolution finer than the gate delay. The basic idea consists in locking the delay line to a certain multiple of clock periods that is not fixed a priori, but is self-adjusted depending on process and operating conditions, and working frequency. In such a way, a wide locking range is achieved with a very compact delay cell structure. The circuit has been used to design a new TDC architecture in which a resolution (time-bin size) of about 16 ps is reached using a 0.35 J..lm CMOS technology. Post-layout simulations show the feasibility of the technique.

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Section: Simulation Resultsmentioning

confidence: 99%

Self-adjusting multiple-period locked delay line For high-resolution multiphase clock generation

Baronti¹,

Lunardini²,

Roncella³

et al. 2005

2005 12th IEEE International Conference on Electronics, Circuits and Systems

Self Cite

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“…Previously many delay elements have been proposed but they do not give linear delay with uniform increase in input vector. Delay elements are used in Phase locked loop (PLL) [1], Time to digital converter (TDC) [2], Digitally controlled oscillator (DCO) [3], Delay locked loop (DLL) [4] etc.…”

Section: Introductionmentioning

confidence: 99%

Decoder and pass transistor based digitally controlled linear delay element

Sharma

Gupta

2014

2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

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With advancement and scaling in Integrated circuit design, the accuracy of clock circuitry plays an increasingly important role. Timing precision is important to reduce the synchronization problem in digital circuits. The precise timing of pulse is also extremely important for designing asynchronous circuits. Delay element is the basic building block for asynchronous circuits. Many circuits of digitally controlled delay elements have been reported in literature. The reported circuits provide a delay which is a non linear function of digital inputs. Non linearity of delay in reported circuits affects the accuracy of time because of which they cannot be used in real world applications. This paper presents a novel circuit of decoder and pass transistor based delay element. The proposed circuit is designed for 3 bits and it provides a delay which is a linear function of digital inputs. The design is implemented in cadence using 180 nm CMOS technology.

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“…A ring oscillator which is activated by the rising edge of the reference clock signal was proposed for clock multiplication in [3]. The code density test (CDT) was proposed to calibrate the delay mismatch in [4], but it takes a long time to get statistical delay information. The delay comparison between multiphase signals was proposed in [5]- [7].…”

Section: Introductionmentioning

confidence: 99%

Process Variation Tolerant All-Digital 90$^{\circ}$ Phase Shift DLL for DDR3 Interface

Kang

Ryu

Jung

et al. 2012

IEEE Trans. Circuits Syst. I

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An all-digital 90 phase shift delay lock loop (DLL) is presented, which is robust against the delay mismatch caused by process variation. Each of the four 90 phase shift blocks accurately aligns its output to a 90 shifted phase using its own ring oscillator and locking delay code. It is analytically proved that the phase shift accuracy of the proposed 90 phase shift block is always higher than that of the conventional all-digital 90 phase shift DLL. The harmonic locking problem is prevented by a ring oscillator and a counter. An area-efficient binary-to-thermometer converter is proposed to reduce the area overhead caused by the delay-line control logic. A fast operating frequency with a finer resolution is achieved through the fine delay range selector and the resistance controlled fine delay unit. The proposed 90 phase shift DLL is implemented using a 45-nm CMOS process. The phase shift accuracy errors at the 90 and 270 phases are 0.43 and 1.01 , respectively, when the maximum locking delay code difference between the four 90 phase shift delay lines corresponds to at 800 MHz. It proves that the DLL corrects the significant phase error caused by process variation. The power consumption is 3.3 mW at 800 MHz.Index Terms-BTC, delay mismatch, digital DLL, multiphase, process variation, 90 phase shift.

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A Self-Calibrating Delay-Locked Delay Line With Shunt-Capacitor Circuit Scheme

Cited by 33 publications

References 13 publications

Self-adjusting multiple-period locked delay line For high-resolution multiphase clock generation

Self-adjusting multiple-period locked delay line For high-resolution multiphase clock generation

Decoder and pass transistor based digitally controlled linear delay element

Process Variation Tolerant All-Digital 90$^{\circ}$ Phase Shift DLL for DDR3 Interface

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