Process Variation Tolerant All-Digital 90$^{\circ}$ Phase Shift DLL for DDR3 Interface

Abstract

An all-digital 90 phase shift delay lock loop (DLL) is presented, which is robust against the delay mismatch caused by process variation. Each of the four 90 phase shift blocks accurately aligns its output to a 90 shifted phase using its own ring oscillator and locking delay code. It is analytically proved that the phase shift accuracy of the proposed 90 phase shift block is always higher than that of the conventional all-digital 90 phase shift DLL. The harmonic locking problem is prevented by a ring oscillator and a counter. An area-efficient binary-to-thermometer converter is proposed to reduce the area overhead caused by the delay-line control logic. A fast operating frequency with a finer resolution is achieved through the fine delay range selector and the resistance controlled fine delay unit. The proposed 90 phase shift DLL is implemented using a 45-nm CMOS process. The phase shift accuracy errors at the 90 and 270 phases are 0.43 and 1.01 , respectively, when the maximum locking delay code difference between the four 90 phase shift delay lines corresponds to at 800 MHz. It proves that the DLL corrects the significant phase error caused by process variation. The power consumption is 3.3 mW at 800 MHz.Index Terms-BTC, delay mismatch, digital DLL, multiphase, process variation, 90 phase shift.

Delay-Lock-Loop-Based Inductorless and Electrolytic Capacitorless Pseudo-Sine-Current Controller in LED Lighting Systems

“…THD and HF can be obtained in (22) and (23), respectively, from the calculation result of (21) In order to find the optimal design in PSC, the indexes of performance are shown in Fig. 7 according to the above derivations.…”

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