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The 68040 Floating Point Unit (FPU) combines three independent state machines, two data paths and over 100,ooO transistors to achieve 8 Mflops peak performance and over 3Mflops Linpack double precision performance at the introductory speed of 25 MHz. The FPU is architecturally divided into three piped stages, the conversion unit (CU), the execution unit (XU), and the normalization unit (NU). The control logic is tested using scan to achieve very high ATPG fault coverage while the data paths were tested using functional patterns.

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