The superscalar architecture of the MC68060

Circello, J.; Edgington, Greg; McCarthy, D.; Schimke, David; Sullivan, S.; Duerden, R.; Hinds, C.N.; Marquette, D.; Sood, L.; Couch, Alva L.; Chow, D.

doi:10.1109/40.372345

Cited by 15 publications

(5 citation statements)

References 5 publications

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“…Thus, unlike VLIW processors where each long instruction contains an operation code for each functional unit, each instruction in superscalar processors specifies only one operation. The hardware looks at several instructions at a time and tries to execute as many instructions simultaneously as it can [20]. To correctly issue multiple instructions to be executed in the same cycle, superscalar processors need to examine and resolve data dependencies between many instructions [21].…”

Section: Superscalar Architecturesmentioning

confidence: 99%

High-performance image computing with modern microprocessors

Basoglu¹,

Kim

Gove³

et al. 1998

Int. J. Imaging Syst. Technol.

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Section: Superscalar Architecturesmentioning

confidence: 99%

High-performance image computing with modern microprocessors

Basoglu¹,

Kim

Gove³

et al. 1998

Int. J. Imaging Syst. Technol.

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“…Parallel fetch and decode is complicated by the need to examine multiple bytes of an instruction before the start address of the next sequential instruction is known. Nevertheless, the economic importance of legacy CISC instruction sets, such as x86, has resulted in several highperformance superscalar variable-length CISC designs [1,4,6,11]. These all convert complex variable-length instructions into fixed-length RISC-like internal "micro-ops".…”

Section: Related Workmentioning

confidence: 99%

“…These all convert complex variable-length instructions into fixed-length RISC-like internal "micro-ops". The Intel P6 microarchitecture can decode three variable-length x86 instructions in parallel, but the second and third instructions must be simple [6]. The P6 takes a brute-force strategy by performing speculative decodes at each byte position, then muxing out the correctly decoded instructions once the lengths of the first and second instructions are determined (further described below).…”

Section: Related Workmentioning

confidence: 99%

Heads and tails

Pan¹,

Asanović²

2001

Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems - CASES '01

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Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and decode. This paper presents a new variable-length instruction format that supports parallel fetch and decode of multiple instructions per cycle, allowing both high code density and rapid execution for high-performance embedded processors. In contrast to earlier schemes that store compressed variable-length instructions in main memory then expand them into fixedlength in-cache formats, the new format is suitable for direct execution from the instruction cache, thereby increasing effective cache capacity and reducing cache power. The new head-and-tails (HAT) format splits each instruction into a fixed-length head and a variable-length tail, and packs heads and tails in separate sections within a larger fixed-length instruction bundle. The heads can be easily fetched and decoded in parallel as they are a fixed distance apart in the instruction stream, while the variable-length tails provide improved code density. A conventional MIPS RISC instruction set is re-encoded in a variable-length HAT scheme, and achieves an average static code compression ratio of 75% and a dynamic fetch ratio (new-bits-fetched/old-bits-fetched) of 75%.

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“…When cleared, these bits allow locking at the way level as opposed to other techniques such as line locking [3] or half-cache locking [1]. Way level locking reduces the control logic area and complexity and still allows way control flexibility.…”

Section: Way Managementmentioning

confidence: 99%

A low power unified cache architecture providing power and performance flexibility (poster session)

Malik

Moyer

Cermak

2000

Proceedings of the 2000 International Symposium on Low Power Electronics and Design - ISLPED '00

200

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Advances in technology have allowed portable electronic devices to become smaller and more complex, placing stringent power and performance requirements on the device's components. The M•CORE M3 architecture was developed specifically for these embedded applications. To address the growing need for longer battery life and higher performance, an 8-Kbyte, 4-way set-associative, unified (instruction and data) cache with programmable features was added to the M3 core. These features allow the architecture to be optimized based on the application's requirements. In this paper, we focus on the features of the M340 cache sub-system and illustrate the effect on power and performance through benchmark analysis and actual silicon measurements.

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The superscalar architecture of the MC68060

Cited by 15 publications

References 5 publications

High-performance image computing with modern microprocessors

High-performance image computing with modern microprocessors

Heads and tails

A low power unified cache architecture providing power and performance flexibility (poster session)

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