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The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64m CPU's, a shared 512KB L2 cache, a DDR memory controller, and integrated UO. All major blocks of the processor are connected together via the ZBbusTM; a high speed split transaction fully coherent multi processor bus.Three Gigabit Ethernet MAC's enable a direct interface to network elements. High-speed system U 0 is provided using AMD's Lightning Data Transport (LDTm) U 0 fabric and a 66MHz PCI bus. The die measures 14.2" by 13.3" in a bulk 0.15pm CMOS technology and has a power dissipation of 13W at 1.2V and 1GHz.

The PA6T-1682M SoC targets applications including compute servers, networking, imaging and storage applications [1]. It integrates two 2GHz Power TM architecture cores, a shared 2MB L2, a coherent crossbar interconnect, two 1066MHz DDR2 64b memory channels, a configurable I/O subsystem able to support two 10Gb and four 1Gb Ethernet MAC, eight PCI Express links of configurable width with an aggregate bandwidth of 6GB/s, and hardware acceleration for cryptography, XOR and network functionalities. The functional block diagram is shown in Fig. 5.5.1. The chip die size is 115mm 2 , implemented in a 65nm triple-V t , dual-oxide 8M CMOS process.The maximum thermal design power is 25W. To achieve this efficiency, the cores have power-saving modes in addition to various active modes, as shown in Fig. 5.5.2. Each core has an independent supply (V DDcpu ), which can be shut down when there is no active workload. This arrangement also enables each core to operate with its own minimum required V DD under the presence of inter-core process and temperature variation. The SRAM arrays have their own V DD supply. The writability of the SRAM cell would otherwise be the limiting factor for the minimum core V DD . The memory and I/O subsystem has its own V DD , which is lower than the technology maximum for additional power savings.Low-voltage operation exacerbates the impact of PVT variations, so the design flow is enhanced to deal with such variations. Monte Carlo simulations are used to characterize critical circuit elements to optimize device sizing. Post processing of the static timing results compensates for the impact of statistical variations on the margin. Low-V t cell swapping into critical paths shapes timing histograms and improves speed yield. In this scheme, noncritical devices with a safe design margin are swapped with a longer channel version to reduce leakage power. Longer channel devices are chosen instead of high V t transistors because of their better voltage scalability and better trade-off of performance versus standby current.Clock gating is extensively used (23,000 instances) as an intrinsic way to implement logic functions and to save power. In-house tools gather flip-flop toggling statistics at the RTL stage of the design and provide early feedback on the effectiveness of clock gating in each functional unit. As the design progresses towards the physical implementation stage, power is re-estimated with actual parasitic extraction using commercial tools. Good correlation was found between the in-house RTL-level tool and the transistor-level simulation accounting for parasitics, as shown in Fig. 5.5.3.Two PLLs provide the variable frequencies for the core and fixed frequencies for the I/O and memory subsystem [2]. Debugging functions such as stretch/squeeze/stop of clocks are built into the balanced H-tree clock distribution. The changing core V DD poses challenges for the clocking scheme. The coherent crossbar and functional units it connects to, such as the L2, are clocked at half the core frequency. Due to ...

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