There are several methods commonly used to locate the area of interest (AOI), such as using layout landmarks, applying laser marks, focus ion beam marks, etc. This paper discusses another method which can improve the job efficiency and cost-effectiveness by introducing the combination of laser marking and laser deprocessing technique (LDT) as a quick way to deprocess the AOI. It further explores LDT to improve the job efficiency and throughput in logic devices to achieve cost-saving targets. An experiment was performed on a 14nm technology node prototype chip that integrated logic and SRAM. The proposed LDT has demonstrated itself to be a useful method to increase the job efficiency by performing in batch and easy to locate the AOI upon loading the sample for SEM inspection. It is also a simple and cost-effective way to delayer comparing to other methodologies.

Conductive thin film residues often referred to as puddles could be challenging fails to detect. A large extant film with no distinct boundaries would make the task more challenging for a comparison between good and bad region. Advanced node 20nm and 14nm technologies mandate use of several conductive thin films in the front end of line processes, and hence a potential for high defects during initial product development stage. Use of other electrical characterization techniques in combination with scanning electron microscopy inspection will be a very powerful tool to detect the root cause affirmatively. Cross-sectional images are necessary to understand the root cause of the fails for corrective actions. This work uses three cases of power supply shorts as a platform to demonstrate the idea, demonstrating a few situations where traditional techniques might reach its limits while the authors depend on additional characterization tools to confidently detect and confirm fails.