A B S T R A C TEscalating density, performance, and (perhaps most importantly) manufacturing requirements associated with ULSI semiconductor wiring, necessitate a metamorphosis in interconnection technology. To meet these needs, an inlaid fully integrated wiring technology called Dual Damascene has been designed and demonstrated at IBMs Essex Junction, Vermont, facility. A subset of the technology's features has been successfully implemented in the manufacture of IBMs 4-Mb DRAM. The Dual Damascene structure achieved is a planar, monolithic-metal interconnect, comprising a vertical metal stud and horizontal metal interconnect, both embedded in an insulator matrix. The complete Dual Damascene technology features a unique process sequence, chemical-mechanical insulator planarization, stacked photolithographic masks, clustered stud and interconnect etch, concurrent stud and interconnect metal fill, and chemical-mechanical metal etchback. In full production, IBMs 4-Mb 200-mm manufacturing implementation uses key elements of this new technology; i.e., chemical-mechanical insulator planarization, concurrent stud and interconnect metal fill, and chemical-mechanical metal etchback. These elements improve manufacturability while maintaining excellent reliability. More progressive Dual Damascene process features such as clustered photolithography and clustered etch, which facilitate self-aligned stud to interconnect structures, are expected to become ULSI necessities as scaling and defect density requirements become still more demanding.

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IBM 90-nm silicon-on-insulator (SOI) technology was used for the key chips in the System z9e processor chipset. Along with system design, optimization of some critical features of this technology enabled the z9e to achieve double the system performance of the previous generation. These technology improvements included logic and SRAM FET optimization, mask fabrication, lithography and wafer processing, and interconnect technology. Reliability improvements such as SRAM optimization and burn-in reliability screen are also described.