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High speed level-1 cache applications demand fast single push-pull driver. and when T and C reset low, the latch will maincycle access times and short cycles. Novel circuits that deliver fast tain the output state. access times and self-resetting CMOS (SRCMOS'.2) techniques An example of how pulse alignment is guaranteed when sigthat deliver fast cycles times are described. Tho key elements for nals arrive at varying times is shown by the SHA in figure 5. It fast access times are: fast signal conversion from static CMOS to has two primary stages: an input amplifier stage and an output SRCMOS and fast signal conversion from SRCMOS to static driver/latch stage. The outputs SL and SR both have low stand-CMOS. These conversions are performed by the input receiver by states and one or the other will pulse high and remain high and output dnver circuits. A two-stage address decode scheme to until the "late select" signal arrives and triggers the 440-1 output minimize gate complexity and a high performance "late select 4-mux. A reset signal is then generated that will reset the SHA to-I" mux in front of the output drivers are also key elements. A latch. In contrast. the input amplifier stage will self-reset inde-"Sense and Hold Amplifier" (SHA) is used to perform pulse alignpendent of the "late select" signal. This allows the input stage to ment with the asynchronous "late select" signal. The critical begin receiving new data from the bit columns even if the output redundancy compare path is designed to be as fast as the primary latch stage had not yet reset. word line decode path in order to minimize any impact on perforIn order to minimize the reset circuitry overhead associated mance. SRCMOS circuitry allows for fast cycle operation without with SRCMOS. extensive sharing of reset circuitry is employed. the use of a centrally controlled clocking scheme. Only the receivThis is accomplished by using "wired-OR" inputs to the reset cirers are clocked and all subsequent circuits are triggered by pulses cuits. For example, the "bit column'' decode path in figure 6 generated from preceding stages. Extensive sharing of reset cirshows the receivers sharing a common reset circuit. The same c u i q is employed to minimize the overhead of SRCMOS. The technique is used for the bit decoders. SRAM includes a programmable "Array-Built-In-Self-Test"To prevent any impact on access time. the redundancy cir-(ABIST) sub-macro which allows extensive test pattem coverage cuitq and the normal address receiving/decoding operation work and access time evaluation at cycle speed. is parallel. For example. during stand-by, the redundant word line The block diagram in figure 1 shows the 288Kb SRAM drivers are enabled and the primary word decode path is disabled. macro (3.33x6.27 mmj. The macm is organized into eight subAt the beginning of each cycle, the redundancy compare circuitry arrays, where each sub-array has 128 word lines by 288 bit colchecks each incoming word address bit for a match against 8 posumns. Also. each sub-array has two redundan...

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