1996 Symposium on VLSI Circuits. Digest of Technical Papers
DOI: 10.1109/vlsic.1996.507741
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A 2 ns access, 500 MHz 288 Kb SRAM macro

Abstract: High speed level-1 cache applications demand fast single push-pull driver. and when T and C reset low, the latch will maincycle access times and short cycles. Novel circuits that deliver fast tain the output state. access times and self-resetting CMOS (SRCMOS'.2) techniques An example of how pulse alignment is guaranteed when sigthat deliver fast cycles times are described. Tho key elements for nals arrive at varying times is shown by the SHA in figure 5. It fast access times are: fast signal conversion from s… Show more

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Cited by 13 publications
(6 citation statements)
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“…The net charge imbalance necessary to upset/flip the cell state equal to , where is the capacitance seen at the storage node of the cell and is the cell differential voltage (which equals the supply voltage for a 6-T SRAM cell). The state-of-the-art planar 6-T SRAM cell in 0.5-m design rules [16], [17] typically has a cell size around 30-35 m and a around 25-30 fC. With 0.25-m design rules, the cell size is expected to shrink to about 10-12 m , with a of 10-15 fC.…”
Section: Static Random Access Memoriesmentioning
confidence: 99%
See 1 more Smart Citation
“…The net charge imbalance necessary to upset/flip the cell state equal to , where is the capacitance seen at the storage node of the cell and is the cell differential voltage (which equals the supply voltage for a 6-T SRAM cell). The state-of-the-art planar 6-T SRAM cell in 0.5-m design rules [16], [17] typically has a cell size around 30-35 m and a around 25-30 fC. With 0.25-m design rules, the cell size is expected to shrink to about 10-12 m , with a of 10-15 fC.…”
Section: Static Random Access Memoriesmentioning
confidence: 99%
“…In most high-performance SRAM's, clocked dual-slope sense amplifiers ( Fig. 4) are used [17], [23]. During sensing, the narrow device is turned on first, so the current increases slowly, allowing differential voltage across the cross-coupled pair to develop and grow.…”
Section: Static Random Access Memoriesmentioning
confidence: 99%
“…Low-power SRAM's also use clocked sense amplifiers to limit the sense power. These are either the current mirror type [16], [17] or cross-coupled latch type [18], [19] designs. In the former, the sense clock turns on the amplifier sometime before the sensing, to set up the amplifier in the high-gain region.…”
Section: Introductionmentioning
confidence: 99%
“…To achieve high performance, the table lookups are implemented using high-speed RAMS [17] or ROMs [19] and the multi-operand adder is implemented using a carry-save adder tree [20], followed by a fast carrypropagate adder [3, ch. 51.…”
Section: Hardware Designmentioning
confidence: 99%